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INT5130CS

Integrated Powerline MAC/PHY Transceiver

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INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

MII_MDCLK

MII_MDIO

tMDI_TSU

DATA

tMDI_TH

Figure 12: MDI Transmit Timing Diagram

MDI DC Characteristics

Parameter

Symbol

Receive Timing

Parameter Name

tMDI_RVAL

MII_MDIO valid from ↑

MII_MDCLK

Transmit Timing

tMDI_TSU

MII_MDIO setup to ↑

MII_MDCLK

Test Condition

Min Max Unit

measured from Vilmax = 0.8V or

measured from Vihmin = 2.0V

0

300 ns

measured from Vilmax = 0.8V or

10

ns

measured from Vihmin = 2.0V

tMDI_TH

MII_MDIO hold to ↑

MII_MDCLK

measured from Vilmax = 0.8V or

measured from Vihmin = 2.0V

10

ns

Table 4: MDI DC Characteristics

MDI Signal Descriptions

Management Data Input/Output

MII_MDIO is a bi-directional signal that is used to transfer status and control information between

the INT5130 and the external host. Control information is driven by the external host

synchronously with respect to MII_MDCLK and is sampled synchronously by the INT5130. Status

information is transferred from the INT5130 to the external host in the same manner.

Management Data Clock

MII_MDCLK is sourced by the external host as the timing reference for transfer of information on

the MII_MDIO signal.

MII Management Register Set

The IEEE 802.3u mandated management data registers for control and status are accessible via the

Management Data Interface (MDI). These registers are also accessible via the industry supported serial

peripheral interface. The MDI Port will only respond to addresses 0xbXX000 when the XX field (MSBits of

the MDI address) match the state of the MDI_ADRSEL[1:0] input signals. These registers can also be

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Rev 8.1

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