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IR2121
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IN
CS
ERR
OUT
Figure 1. Input/Output Timing Diagram
VCC
OUT
IR2121
4
Figure 2. Switching Time Test Circuit
IN
ton
50%
50%
tr
90%
toff
tf
90%
OUT
10%
10%
Figure 3. Switching Time Waveform Definitions
CS
OUT
50%
tcs
90%
Figure 4. ERR Shutdown Waveform Definitions
50%
CS
tcs
HO
90%
Figure 5. CS Shutdown Waveform Definitions
B-96 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL
50%
CS
terr
ERR
50%
1.8V
dt
dt = C × dV = C × 1.8V
IERR
100 uA
Figure 6. CS to ERR Waveform Definitions
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