IR3086 Ver la hoja de datos (PDF) - International Rectifier
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IR3086 Datasheet PDF : 15 Pages
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IR3086
PWM Control Method
The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for
the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the
slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change with
the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to
variations in the silver box output voltage or due to drops in the PCB related to changes in load current.
CONTROL IC
50%
DUTY
CYCLE
RAMP GENERATOR
VPEAK
VVALLEY
+
VBIAS
REGULATOR
-
VDAC
ERROR
AMP
IFB
IROSC
VDRP
AMP
RMPOUT
VBIAS
VDAC
VOSNS-
EAOUT
FB
VDRP
IIN
RVFB
RDRP
BIASIN
RAMPIN+
RRAMP1
RAMPIN-
RRAMP2
R PW MR MP
EAIN
PWMRMP
CPWMRMP
SCOMP
CSCOMP
ISHARE
DACIN
SYSTEM
REFERENCE
VOLTAGE
CLOCK
PULSE
GENERATOR
PHASE IC
PWM
LATCH
S
PWM
COMPARATOR
-
+
RESET
DOMINANT
R
RAMP
SLOPE
ADJUST
SHARE
ADJUST
ERROR
AMP
10K
ENABLE
RAMP
DISCHARGE
CLAMP
+
20mV
-
O% DUTY
CYCLE
COMPARATOR
X
0.91
CURRENT
SENSE
AMP
X34
GATEH
GATEL
CSIN+
CCS RCS
CSIN-
BIASIN
RAMPIN+
RRAMP1
RAMPIN-
RRAMP2
R PW MR MP
EAIN
PWMRMP
CPWMRMP
SCOMP
CSCOMP
ISHARE
DACIN
SYSTEM
REFERENCE
VOLTAGE
CLOCK
PULSE
GENERATOR
PHASE IC
PWM
LATCH
S
PWM
COMPARATOR
-
+
RESET
DOMINANT
R
RAMP
SLOPE
ADJUST
SHARE
ADJUST
ERROR
AMP
10K
ENABLE
RAMP
DISCHARGE
CLAMP
+
20mV
-
O% DUTY
CYCLE
COMPARATOR
X
0.91
CURRENT
SENSE
AMP
X34
GATEH
GATEL
CSIN+
CCS RCS
CSIN-
Figure 2 – PWM Block Diagram
VIN
VOSNS+
VOUT
COUT
GND
VOSNS-
Frequency and Phase Timing Control
An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty cycle
triangle waveform with peak and valley voltages of approximately 5V and 1V. This signal is used to program both the
switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RRAMP1
and RRAMP2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the
Phase ICs detects the crossing of the oscillator waveform with the voltage generated by the resistor divider and
triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing
potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note that both slopes of
the triangle waveform can be used for synchronization by swapping the RAMP + and – pins.
Page 7 of 15
9/1/03
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