IR3088 Ver la hoja de datos (PDF) - International Rectifier
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IR3088 Datasheet PDF : 34 Pages
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IR3088
PWM Control Method
The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the
slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change
with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change
due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes
in load current.
CONTROL IC
50%
DUTY
CYCLE
RAMP GENERATOR
VPEAK
VVALLEY
+
VBIAS
REGULATOR
-
VDAC
ERROR
AMP
IFB
IROSC
VDRP
AMP
RMPOUT
VBIAS
VDAC
VOSNS-
EAOUT
FB
VDRP
IIN
RVFB
RDRP
BIASIN
RAMPIN+
RPHS1
RPHS2
RPWMRMP
RAMPIN-
EAIN
PWMRMP
CPWMRMP
SCOMP
CSCOMP
ISHARE
DACIN
SYSTEM
REFERENCE
VOLTAGE
CLOCK
PULSE
GENERATOR
PHASE IC
PWM
LATCH
S
PWM
COMPARATOR
-
+
RESET
DOMINANT
R
SHARE
ADJUST
ERROR
AMPLIFIER
ENABLE
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
X
0.91
+
10K
20mV
-
CURRENT
SENSE
AMPLIFIER
X34
GATEH
GATEL
CSIN+
CCS RCS
CSIN-
RPHS1
RPHS2
RPWMRMP
BIASIN
RAMPIN+
RAMPIN-
EAIN
PWMRMP
CPWMRMP
SCOMP
CSCOMP
ISHARE
DACIN
SYSTEM
REFERENCE
VOLTAGE
CLOCK
PULSE
GENERATOR
PHASE IC
PWM
LATCH
S
PWM
COMPARATOR
-
+
RESET
DOMINANT
R
SHARE
ADJUST
ERROR
AMPLIFIER
ENABLE
RAMP
DISCHARGE
CLAMP
BODY
BRAKING
COMPARATOR
X
0.91
+
10K
20mV
-
CURRENT
SENSE
AMPLIFIER
X34
GATEH
GATEL
CSIN+
CCS RCS
CSIN-
Figure 2. PWM Block Diagram
VIN
VOSNS+
VOUT
COUT
GND
VOSNS-
Frequency and Phase Timing Control
An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty
cycle triangle waveform with peak and valley voltages of approximately 5V and 1V respectively. This signal is used
to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by
resistor divider RPHS1 and RPHS2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A
comparator in the Phase ICs detects the crossing of the oscillator waveform over the voltage generated by the
resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS
voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note
that both slopes of the triangle waveform can be used for phase timing by swapping the RMPIN+ and RMPIN– pins,
as shown in Figure 2.
Page 7 of 34
9/30/04
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