IS42RM Ver la hoja de datos (PDF) - Integrated Silicon Solution
Número de pieza
componentes Descripción
Lista de partido
IS42RM Datasheet PDF : 33 Pages
| |||
IS42SM/RM/VM16400K
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of
output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m
clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m -
1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the
clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to
two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6. Reserved states should not be used
as unknown operation or incompatibility with future versions may result.
Figure6: CAS Latency
T0
T1
T2
T3
CLK
COMMAND
DQ
READ
NOP
tLZ
tAC
CAS Latency=2
NOP
tOH
Dout
CLK
COMMAND
T0
READ
DQ
T1
T2
T3
T4
NOP
NOP
tLZ
tAC
CAS Latency=3
NOP
tOH
Dout
DON’T CARE
UNDEFINED
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved
for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
Rev. A | August 2012
www.issi.com - DRAM@issi.com
10
Share Link: 