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IS61C1024-20T

128K x 8 HIGH-SPEED CMOS STATIC RAM

Integrated Silicon Solution 

IS61C1024

IS61C1024L

AC WAVEFORMS

WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )

t WC

ADDRESS

t SA

CE1

VALID ADDRESS

t SCE1

t SCE2

ISSI ®

t HA

CE2

WE

DOUT

DIN

DATA UNDEFINED

t AW

t PWE1

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)

ADDRESS

OE

t WC

VALID ADDRESS

t HA

CE2_WR1.eps

CE1

CE2

LOW

HIGH

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE1

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DIN

DATAIN VALID

CE2_WR2.eps

Notes:

1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to

the rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE = VIH.

8

SR028-1J

11/03/98

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