ISL8484(2006) Ver la hoja de datos (PDF) - Intersil
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ISL8484
(Rev.:2006)
(Rev.:2006)
Intersil
ISL8484 Datasheet PDF : 13 Pages
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ISL8484
Test Circuits and Waveforms
V+
LOGIC
INPUT
0V
50%
tOFF
tr < 5ns
tf < 5ns
SWITCH
INPUT
VNO
SWITCH
OUTPUT 0V
VOUT
90%
tON
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
C
SWITCH
INPUT
LOGIC
INPUT
NO OR NC
IN
GND
COM
VOUT
RL
CL
50Ω 35pF
Repeat test for all switches. CL includes fixture and stray
capacitance.
VOUT
=
V(NO or NC)
------------R-----L-------------
RL + R(ON)
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
FIGURE 1B. TEST CIRCUIT
V+
C
SWITCH
OUTPUT
VOUT
LOGIC ON
INPUT
∆VOUT
OFF
V+
ON
0V
RG
NO OR NC
COM
VG
GND
IN
LOGIC
INPUT
Q = ∆VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
Repeat test for all switches.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
VOUT
CL
V+
C
V+
LOGIC
INPUT
0V
NO
VNX
NC
IN
COM
VOUT
RL
CL
50Ω
35pF
SWITCH
OUTPUT
VOUT 0V
90%
LOGIC
INPUT
tD
GND
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
6
FN6128.2
September 13, 2006
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