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ISP1130

Universal Serial Bus compound hub with integrated keyboard controller

Philips Electronics 

Philips Semiconductors

ISP1130

USB compound hub with keyboard controller

6.9 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream

using a 4× oversampling principle. It is able to track jitter and frequency drift as

specified by the USB Specification Rev. 1.1.

6.10 Voltage regulator

A 5 to 3.3 V DC-DC regulator is integrated on-chip to supply the analog transceiver

and internal logic. This can also be used to supply the terminal 1.5 kΩ pull-up resistor

on the D+ line of the upstream connection.

6.11 PLL clock multiplier

A 6 to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This

allows for the use of low-cost 6 MHz crystals. The low crystal frequency also

minimizes Electro-Magnetic Interference (EMI). The PLL requires no external

components.

6.12 Overcurrent detection

An overcurrent detection circuit for downstream ports has been integrated on-chip. It

is self-reporting, resets automatically, has a low trip time and requires no external

components. The ISP1130 supports individual overcurrent detection.

6.13 Power-on reset

The ISP1130 has an internal power-on reset circuit, which generates a reset pulse

when the supply voltage is switched on and when the supply voltage drops below a

predetermined threshold value (see Table 89).

6.14 I2C-bus interface

A serial I2C-bus interface (single master or slave, bit rate up to 400 kHz) is provided

to read vendor ID, product ID and other configuration data from an external EEPROM

(e.g., Philips PCF8582 or equivalent). For more information, see Section 11.

The I2C-bus interface timing is programmable and complies with the standard mode

and the Fast mode of operation as described in The I2C-bus and how to use it, order

number 9398 393 40011.

9397 750 06895

Objective specification

Rev. 01 — 23 March 2000

© Philips Electronics N.V. 2000. All rights reserved.

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