IW4011B Ver la hoja de datos (PDF) - Estek Electronics Co. Ltd

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IW4011B

NAND gates provide the system designer with direct implementation of the NAND function

Estek Electronics Co. Ltd 

Absolute Maximum Ratings

Symbol

Parameter

VCC DC Supply Voltage (Referenced to GND)

VIN

DC Input Voltage (Referenced to GND)

IIN

DC Input Current, per Pin

PD

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

PD

Power Dissipation per Output Transistor

Tstg Storage Temperature

IW4011B

Value

Unit

-0.5 to +20

V

-0.5 to V CC +0.5

V

10

mA

750

mW

500

100

mW

-65 to +150

C

TL

Lead Temperature, 1 mm from Case for 10 Seconds

260

C

(Plastic DIP or SOIC Package)

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/ C from 65 to 125C

SOIC Package: - 7 mW/ C from 65to 125C

Recommended Operating Conditions

Symbol

Parameter

Min

Max

Unit

VCC

DC Supply Voltage (Referenced to GND)

3.0

18

V

VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

0

CC

V

V

-55

+125

C

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages

to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND (VIN or

VOUT) VCC .

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs

must be left open.

BEIJING ESTEK ELECTRONICS CO.,LTD

2

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