AIC1570-CS Ver la hoja de datos (PDF) - Analog Intergrations
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AIC1570-CS
Analog Intergrations
AIC1570-CS Datasheet PDF : 18 Pages
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AIC1570
Layout Considerations
Any inductance in the switched current path
generates a large voltage spike during the
switching interval. The voltage spikes can
degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful
component selection and tight layout of critical
components, and short, wide metal trace
minimize the voltage spike.
1) A ground plane should be used. Locate the
input capacitors (CIN) close to the power
switches. Minimize the loop formed by CIN,
the upper MOSFET (Q1) and the lower
MOSFET (Q2) as possible. Connections
should be as wide as short as possible to
minimize loop inductance.
2) The connection between Q1, Q2 and output
inductor should be as wide as short as
practical. Since this connection has fast
voltage transitions will easily induce EMI.
3) The output capacitor (COUT) should be
located as close the load as possible.
Because minimize the transient load
magnitude for high slew rate requires low
inductance and resistance in circuit board
4) The AIC1570 is best placed over a quiet
ground plane area. The GND pin should be
connected to the groundside of the output
capacitors. Under no circumstances should
GND be returned to a ground inside the CIN,
Q1, Q2 loop. The GND and PGND pins
should be shorted right at the IC. This help to
minimize internal ground disturbances in the
IC and prevents differences in ground
potential from disrupting internal circuit
operation.
5) The wiring traces from the control IC to the
MOSFET gate and source should be sized to
carry 1A current. The traces for OUT2 need
only be sized for 0.5A. Locate COUT2 close to
the AIC1570 IC.
6) The Vcc pin should be decoupled directly to
GND by a 1uF ceramic capacitor, trace
lengths should be as short as possible.
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