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LTC1553

5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® II Processor

Linear Technology 

LTC1553

PIN FUNCTIONS

G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET,

Q2. This output will swing from PVCC to GND. It will always

be low when G1 is high or when the output is disabled. To

prevent undershoot during a soft start cycle, G2 is held low

until G1 first goes high.

PVCC (Pin 2): Power Supply for G1 and G2. PVCC must be

connected to a potential of at least VIN + VGS(ON)Q1. If

VIN = 5V, PVCC can be generated using a simple charge

pump connected to the switching node between Q1 and

Q2 (see Figure 7), or it can be connected to an auxiliary 12V

supply if one exists. For applications where VIN = 12V,

PVCC can be generated using a 17V charge pump (see

Figure 9).

GND (Pin 3): Power Ground. GND should be connected to

a low impedance ground plane in close proximity to the

source of Q2.

SGND (Pin 4): Signal Ground. SGND is connected to the

low power internal circuitry and should be connected to

the negative terminal of the output capacitor where it

returns to the ground plane. GND and SGND should be

shorted right at the LTC1553.

VCC (Pin 5): Power Supply. Power for the internal low

power circuity. VCC should be wired separately from the

drain of Q1 if they share the same supply. A 10µF bypass

capacitor is recommended from this pin to SGND.

SENSE (Pin 6): Output Voltage Pin. Connect to the positive

terminal of the output capacitor. There is an internal 120k

resistor connected from this pin to SGND. SENSE is a very

sensitive pin; for optimum performance, connect an exter-

nal 0.1µF capacitor from this pin to SGND. By connecting

a small external resistor between the output capacitor and

the SENSE pin, the initial output voltage can be raised

slightly. Since the internal divider has a nominal imped-

ance of 120kΩ, a 1200Ω series resistor will raise the

nominal output voltage by 1%. If an external resistor is

used, the value of the 0.1µF capacitor on the SENSE pin

must be greatly reduced or loop phase margin will suffer.

Set a time constant for the RC combination of approxi-

mately 0.1µs. So, for example, with a 1200Ω resistor, set

C = 83pF. Use a standard 100pF capacitor.

IMAX (Pin 7): Current Limit Threshold. Current limit is set

by the voltage drop across an external resistor connected

between the drain of Q1 and IMAX. There is a 180µA internal

pull-down at IMAX.

IFB (Pin 8): Current Limit Sense Pin. Connect to the

switching node between the source of Q1 and the drain of

Q2. If IFB drops below IMAX when G1 is on, the LTC1553

will go into current limit. The current limit circuit can be

disabled by floating IMAX and shorting IFB to VCC through

an external 10k resistor. For VIN = 12V, a 15V Zener diode

from IFB to GND is recommended to prevent the voltage

spike at IFB from exceeding the maximum voltage rating.

SS (Pin 9): Soft Start. Connect to an external capacitor to

implement a soft start function. During moderate overload

conditions, the soft start capacitor will be discharged

slowly in order to reduce the duty cycle. In hard current

limit, the soft start capacitor will be forced low immedi-

ately and the LTC1553 will rerun a complete soft start

cycle. CSS must be selected such that during power-up the

current through Q1 will not exceed the current limit value.

COMP (Pin 10): External Compensation. The COMP pin is

connected directly to the output of the error amplifier and

the input of the PWM comparator. An RC + C network is

used at this node to compensate the feedback loop to

provide optimum transient response.

OT (Pin 11): Over-Temperature Fault. OT is an open-drain

output and will be pulled low if OUTEN is less than 2V. If

OUTEN = 0, OT pulls low.

FAULT (Pin 12): Overvoltage Fault. FAULT is an open-

drain output. If VOUT reaches 15% above the nominal

output voltage, FAULT will go low and G1 and G2 will be

disabled. Once triggered, the LTC1553 will remain in this

state until the power supply is recycled or the OUTEN pin

is toggled. If OUTEN = 0, FAULT floats or is pulled high by

an external resistor.

PWRGD (Pin 13): Power Good. This is an open-drain

signal to indicate validity of output voltage. A high indi-

cates that the output has settled to within ±5% of the rated

output for more than 1ms. PWRGD will go low if the output

is out of regulation for more than 500µs. If OUTEN = 0,

PWRGD pulls low.

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