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SAA7196

Digital video decoder, Scaler and Clock generator circuit (DESCPro)

Philips Electronics 

Philips Semiconductors

Digital video decoder, Scaler and Clock

generator circuit (DESCPro)

Product specification

SAA7196

1 FEATURES

• Digital 8-bit luminance input [video (Y) or CVBS]

• Digital 8-bit chrominance input [CVBS or C from CVBS,

Y/C, S-Video (S-VHS or Hi8)]

• Luminance and chrominance signal processing for main

standards PAL, NTSC and SECAM

• Horizontal and vertical sync detection for all standards

• User programmable luminance peaking for aperture

correction

• Compatible with memory-based features (line-locked

clock, square pixel)

• Cross colour reduction by chrominance comb-filtering

for NTSC or special cross-colour cancellation for

SECAM

• UV signal delay lines for PAL to correct chrominance

phase errors

• Square-pixel format with 768/640 active samples per

line

• The bidirectional expansion port (YUV-bus) supports

data rates of 780 × fH (NTSC) and 944 × fH (PAL,

SECAM) in 4 : 2 : 2 format

• Brightness, contrast, hue and saturation controls for

scaled outputs

• Down-scaling of video windows with 1023 active

samples per line and 1023 active lines per frame to

randomly sized windows

• 2D data processing for improved signal quality of scaled

luminance data, especially for compression applications

• Chroma key (α-generation)

• YUV to RGB conversation including anti-gamma

ROM tables for RGB

• 16-word output FIFO (32-bit words)

• Output configurable for 32-, 24- and 16-bit

video data bus

• Scaled 16-bit 4 : 2 : 2 YUV output

• Scaled 15-bit RGB (5-5-5+α) and 24-bit (8-8-8+α)

output

• Scaled 8-bit monochrome output

• Line increment, field sequence (odd/even,

interlace/non-interlaced) and vertical reset control for

easy memory interfacing

• Output of discontinuous data bursts of scaled video data

or continuous data output with corresponding qualifier

signals

• Real-time status information

• I2C-bus control

• Only one crystal of 26.8 MHz required

• Clock generator on chip.

2 GENERAL DESCRIPTION

The CMOS circuit SAA7196, digital video decoder, scaler

and clock generator (DESCPro), is a highly integrated

circuit for DeskTop Video applications. It combines the

functions of a digital multistandard decoder (SAA7191B),

a digital video scaler (SAA7186) and a clock generator

(SAA7197).

The decoder is based on the principle of line-locked clock

decoding. It runs at square-pixel frequencies to achieve

correct aspect ratio. Monitor controls are provided to

ensure best display.

Four data ports are supported:

• Port CVBS7 to CVBS0 of input interface; used in Y/C

mode (see Fig.1) to decode digitized luminance and

chrominance signals (digitized in two external ADCs).

In normal mode, only this input port is used and only one

ADC is necessary (see Fig.4)

• Port CHR7 to CHR0 of input interface; used in Y/C

mode (see Fig.1) to decode digitized luminance and

chrominance signals (digitized in two external ADCs)

• 32-bit VRAM output port; interface to the video memory.

It outputs the down-scaled video data; different formats

and operation modes are supported by this circuit

• 16-bit expansion port; this is a bidirectional port.

In general, it establishes the digital YUV as known from

the SAA71x1 family of digital decoders. In addition, the

expansion port is configurable to send data from the

decoder unit or to accept external data for input into the

scaler. In input mode the clock rate and/or the sync

signals may be delivered by the external data source.

Decoder and scaler units can run at different clock rates.

The decoder processing always operates with a Line

Locked Clock (LLC). This clock is derived from the CVBS

signal and is suited best for memory based video

processing; the LLC clock is always present. The scaler

clock may be driven by the LLC clock or by an external

clock depending on the configuration of the expansion

port.

1996 Nov 04

3

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