KSZ8841-PMQL(2006) Ver la hoja de datos (PDF) - Micrel
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KSZ8841-PMQL Datasheet PDF : 74 Pages
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Micrel, Inc.
KSZ8841-PMQL
Pin
Number
72
Pin
Name
STOPN
73
IDSEL
74
DEVSELN
75
REQN
76
GNTN
77
PERRN
78
DGND
79
VDDIO
80
SERRN
81
NC
82
NC
83
NC
84
NC
85
CBE3N
86
CBE2N
87
CBE1N
88
CBE0N
89
PAD31
90
DGND
91
VDDC
92
VDDIO
93
PAD30
94
PAD29
95
PAD28
96
PAD27
97
PAD26
Type
Pin Function
I/O
PCI Stop
This signal is asserted low by the target device to request the master device to stop the
current transaction.
I/O
PCI Initialization Device Select
This signal is used to select the KSZ8841-PMQL during configuration read and write
transactions. Active high.
I/O
PCI Device Select
This signal is asserted low when it is selected as a target during a bus transaction. As a
bus master, the KSZ8841-PMQL samples this signal to insure that a PCI target
recognizes the destination address for the data transfer.
O
PCI Bus Request
The KSZ8841-PMQL will assert this signal low to request PCI bus master operation.
I
PCI Bus Grant
This signal is asserted low to indicate to the KSZ8841-PMQL that it has been granted
the PCI bus master operation.
I/O
PCI Parity Error
The KSZ8841-PMQL as a master or target will assert this signal low to indicate a parity
error on any incoming data. As a bus master, it will monitor this signal on all write
operations.
Gnd Digital ground
P
3.3V digital I/O VDD
O
PCI System Error
This system error signal is asserted low by the KSZ8841-PMQL. This signal is used to
report address parity errors.
—
No connect
—
No connect
—
No connect
—
No connect
I/O
Command and Byte Enable
I/O
These signals are multiplexed on the same PCI pins. During the address phase, these
I/O
lines define the bus command. During the data phase, these lines are used as Byte
Enables, The Byte enables are valid for the entire data phase and determine which byte
I/O
lanes carry meaningful data.
I/O
PCI Address / Data 31
Address and data are multiplexed on the all of the PAD pins. The PAD pins carry the
physical address during the first clock cycle of a transaction, and carry data during the
subsequent clock cycles.
Gnd Digital core ground
P
1.2V digital core VDD
P
3.3V digital I/O VDD
I/O
PCI Address / Data 30
I/O
PCI Address / Data 29
I/O
PCI Address / Data 28
I/O
PCI Address / Data 27
I/O
PCI Address / Data 26
June 2006
12
M9999-061206-1.2
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