KSZ8842-PMQL Ver la hoja de datos (PDF) - Micrel

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Lista de partido

KSZ8842-PMQL

2-Port Ethernet Switch with PCI Interface

Micrel 

Micrel, Inc.

KSZ8842-PMQL/PMBL

Ball

Number

K2

Ball

Name

IRDYN

Type

I/O

H3

TRDYN

I/O

J3

STOPN I/O

K3

IDSEL

I/O

H4

DEVSELN I/O

J4

REQN

O

K4

GNTN

I

H5

PERRN I/O

J5

SERRN O

K5

CBE3N

I

K6

CBE2N

I

J6

CBE1N

I

H6

CBE0N

I

K7

PAD31

I/O

J7

PAD30

I/O

H7

PAD29

I/O

K8

PAD28

I/O

J8

PAD27

I/O

H8

PAD26

I/O

K9

PAD25

I/O

J9

PAD24

I/O

K10

PAD23

I/O

Ball Function

PCI Initiator Ready

As a bus master, this signal is asserted low to indicate valid data phases on PAD [31:0]

during write data phases, indicates it is ready to accept data during read data phases. As a

target, it’ll monitor this IRDYN signal that indicates the master has put the data on the bus.

PCI Target Ready

As a bus target, this signal is asserted low to indicate valid data phases on PAD [31:0] during

read data phases, indicating it is ready to accept data during write data phases. As a master,

it will monitor this TRDYN signal that indicates the target is ready for data during read/write

operation.

PCI Stop

This signal is asserted low by the target device to stop the current transaction

PCI Initialization Device Select.

This signal is used to select the KSZ8842-PMQL/PMBL during configuration read and write

transactions.

PCI Device Select

This signal is asserted low when it is selected as a target during a bus transaction. As a bus

master, the KSZ8842-PMBL samples this signal to insure that the destination address for the

data transfer is recognized by a PCI target.

PCI Request

The KSZ8842-PMBL will assert this signal low to request PCI bus master operation.

PCI Grant

This signal is asserted low to indicate to the KSZ8842-PMBL that it has been granted the PCI

bus master operation.

PCI Parity Error

The KSZ8842-PMBL as a master or target will assert this signal low to indicate a parity error

on any incoming data. As a bus master, it will monitor this signal on all write operations.

PCI System Error

This system error signal is asserted low by the KSZ8842-PMBL.This signal is used to report

address parity errors.

Command and Byte Enable

These signals are multiplexed on the same PCI pins. During the address phase, these lines

define the bus command. During the data phase, these lines are used as Byte Enables. The

Byte enables are valid for the entire data phase and determine which byte lanes carry

meaningful data.

PCI Address / Data 31

Address and data are multiplexed on the all of the PAD balls. The PAD pins carry the

physical address during the first clock cycle of a transaction, and carry data during the

subsequent clock cycles.

PCI Address / Data 30

PCI Address / Data 29

PCI Address / Data 28

PCI Address / Data 27

PCI Address / Data 26

PCI Address / Data 25

PCI Address / Data 24

PCI Address / Data 23

October 2007

18

M9999-100207-1.5

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