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L6566B

Multi-mode controller for SMPS

STMicroelectronics 

L6566B

Pin settings

Table 1. Pin functions (continued)

N° Pin

Function

Supply voltage of both the signal part of the IC and the gate driver. The internal

high voltage generator charges an electrolytic capacitor connected between this

pin and GND (pin 3) as long as the voltage on the pin is below the turn-on threshold

5

Vcc

of the IC, after that it is disabled and the chip is turned on. The IC is disabled as the

voltage on the pin falls below the UVLO threshold. This threshold is reduced at light

load to counteract the natural reduction of the self-supply voltage. Sometimes a

small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias

voltage for the signal part of the IC.

Frequency modulation input. When FF mode operation is selected, a capacitor

connected from this pin to GND (pin 3) is alternately charged and discharged by

internal current sources. As a result, the voltage on the pin is a symmetrical

6

FMOD

triangular waveform with the frequency related to the capacitance value. By

connecting a resistor from this pin to pin 13 (OSC) it is possible to modulate the

current sourced by the OSC pin and then the oscillator frequency. This modulation

is to reduce the peak value of EMI emissions by means of a spread-spectrum

action. If the function is not used, the pin will be left open.

Input to the PWM comparator. The current flowing in the MOSFET is sensed

through a resistor, the resulting voltage is applied to this pin and compared with an

internal reference to determine MOSFET’s turn-off. The pin is equipped with 150 ns

min. blanking time after the gate-drive output goes high for improved noise

7

CS immunity. A second comparison level located at 1.5 V latches the device off and

reduces its consumption in case of transformer saturation or secondary diode short

circuit. The information is latched until the voltage on the Vcc pin (5) goes below

the UVLO threshold, hence resulting in intermittent operation. A logic circuit

improves sensitivity to temporary disturbances.

IC’s latched disable input. Internally the pin connects a comparator that, when the

voltage on the pin exceeds 4.5 V, latches off the IC and brings its consumption to a

lower value. The latch is cleared as the voltage on the Vcc pin (5) goes below the

8

DIS

UVLO threshold, but the HV generator keeps the Vcc voltage high (see pin 1

description). It is then necessary to recycle the input power to restart the IC. For a

quick restart pull pin 16 (AC_OK) below the disable threshold (see pin 16

description). Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-

up. Ground the pin if the function is not used.

Control input for loop regulation. The pin will be driven by the phototransistor

(emitter-grounded) of an optocoupler to modulate its voltage by modulating the

current sunk. A capacitor placed between the pin and GND (3), as close to the IC

9

COMP

as possible to reduce noise pick-up, sets a pole in the output-to-control transfer

function. The dynamics of the pin is in the 2.5 to 5 V range. A voltage below an

internally defined threshold activates burst-mode operation. The voltage at the pin

is bottom-clamped at about 2 V. If the clamp is externally overridden and the

voltage is pulled below 1.4 V the IC will shut down.

An internal generator furnishes an accurate voltage reference (5 V ± 2 %) that can

be used to supply few mA to an external circuit. A small film capacitor (0.1 µF typ.),

10

VREF

connected between this pin and GND (3), is recommended to ensure the stability of

the generator and to prevent noise from affecting the reference. This reference is

internally monitored by a separate auxiliary reference and any failure or drift will

cause the IC to latch off.

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