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L6997D Ver la hoja de datos (PDF) - STMicroelectronics

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L6997D Datasheet PDF : 23 Pages
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L6997
be supposed linear function of the time.
Eq 8
IL ( t ,C S S )
=
-(--R----i--l-i--m----/--R----d---s---o---n--------K----C--------I--S---S--------t--)-
(∆VSS CSS)
so the output voltage is given by:
Eq 9
Vo u t ( t ,CS S)
=
Q-----(---t--,--C----S----S----)
Cout
=
(---R-----i-l-i--m----/--R-----d---s---o---n-------K----C--------I--S----S-------t--2---)-
(Cout ⋅ ∆VSS CSS 2 )
calling Vout as the Vout final value, the output charging time can be estimated as:
Eq 10
Iout(CSS) =
-(--V----o---u---t------C-----o---u---t----------V----S---S--------C-----S---S--------2----) 0.5
(Rilim /Rdson KC ISS)
the minimum CSS value is given imposing this condition:
Eq 11 Tout =Tuvp
1.5 Current limit
The current limit comparator senses the inductor current through the low side MOSFET RDSON drop and com-
pares this value with the ILIM pin voltage value. While the current is above the current limit value, the control
inhibits the one-shot start.
To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current
depends on the inductor value, VIN VOUT and switching frequency.
The average output current in current limit is given by:
Eq 12
IOUTCL
=
Imax
valley
+
----I
2
Thus, to set the current threshold, choose RILIM according to the following equation:
Eq 13
m ax valley
=
--R----I--L---i--m----
R d so n
KILIM
In current limit the system keeps the current constant until the output voltage meets the undervolatge threshold.
The negative valley current limit, for the sink mode, is set automatically at the same value of the positive valley
current limit. The average negative current limit differs from the positive average current limit by the ripple cur-
rent; this difference is due to the valley control technique.
The system accuracy is function of the exactness of the resistance connected to ILIM pin and the low side MOS-
FET RDSON accuracy. Moreover the voltage on ILIM pin must range between 10mV and 1V to ensure the sys-
tem linearity.
Figure 6. Current limit schematic
To inductor
LS
PGN
PHASE
R
D
ILIM
Current
Comparator
5µA
Positive and negative current limit
To
logic
10/23

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