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L6997S

STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONS

STMicroelectronics 

L6997S

4.6 Protection and fault

The load protection is realized by using the VSENSE pin. Both OVP and UVP are latched, and the fault condition

is indicated by the PGOOD and the OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ)

of the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched:

low side MOSFET and, high side MOSFET are turned off and PGOOD goes low. In case the system detects an

overvoltage the OVP pin goes high.

To recover the functionality the device must be shut down and restarted the SHDN pin, or by removing the sup-

ply, and restarting the devicewith the correct sequence.

4.7 Drivers

The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran-

sitions. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating

driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The

drivers have the adaptive anti-cross-conduction protection, which prevents from having bothhigh side and low

side MOSFET on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET

is turned off the voltage on the PHASE pin begins to fall; the low side MOSFET is turned on only when the volt-

age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage

reaches 500mV. This is important since the driver can work properly with a large range of external power MOS-

FETS.

The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the

MOSFET gate charge the switching frequency and the driver voltage. So the power dissipation of the device is

function of the external power MOSFET gate charge and switching frequency.

Pdriver = Vcc ⋅ QgTOT ⋅ FSW (14)

The maximum gate charge values for the low side and high side are given by:

QMAXHS

=

f--S----W-----0-

fSW

⋅

75

nC

(15)

QMAXLS

=

f--S----W-----0-

fSW

⋅

125 n C

(16)

Where fSW0 = 500Khz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG

can be higher.

For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;

in this case the maximum value is QMAXLS = 125nC.

The low side driver has been designed to have a low resistance pull-down transistor, approximately 0.5 ohms.

This prevents undesired LS MOSFET Turn On during the fast rise-time of the pin PHASE, due to the Miller ef-

fect.

When the 3.3V bus is used to supply the drivers, ULTRA LOGIC LEVEL MOSFETs should be selected , to be

sure that the MOSFETs work in properly way.

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