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LAN83C183

10/100 Mbps TX/FX/10BT Fast Ethernet Physical Layer Device (PHY)

SMSC -> Microchip 

The MII interface contains the following signals:

• Transmit data bits (TXD[3:0])

• Transmit clock (TX_CLK)

• Transmit enable (TX_EN)

• Transmit error (TX_ER)

• Receive data bits (RXD[3:0])

• Receive clock (RX_CLK)

• Carrier sense (CRS)

• Receive data valid (RX_DV)

• Receive data error (RX_ER)

• Collision (COL)

The transmit and receive clocks operate at 25 MHz in 100 Mbits/s mode.

On the transmit side, the TX_CLK output runs continuously at 25 MHz. When no data

is to be transmitted, TX_EN must be deasserted. While TX_EN is deasserted,

TX_ER and TXD[3:0] are ignored and no data is clocked into the device. When

TX_EN is asserted on the rising edge of TX_CLK, data on TXD[3:0] is clocked into

the device on the rising edge of the TX_CLK output clock. TXD[3:0] input data is

nibble wide packet data whose format must be the same as specified in IEEE 802.3

and shown in Figure 1.3. When all data on TXD[3:0] has been latched into the

device, TX_EN must be deasserted on the rising edge of TX_CLK.

TX_ER is also clocked in on the rising edge of TX_CLK. TX_ER is a transmit error

signal. When this signal is asserted, the device substitutes an error nibble in place

of the normal data nibble that was clocked in on TXD[3:0]. The error nibble is defined

to be the /H/ symbol, which is defined in IEEE 802.3 and shown in Table 1.3.

SMSC DS – LAN83C183

17

Rev. 12/14/2000

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