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LAN91C111I-NE

10/100 Non-PCI Ethernet Single Chip MAC + PHY

SMSC -> Microchip 

Chapter 16 Revision History

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Table 16.1 Customer Revision History

REVISION LEVEL & DATE SECTION/FIGURE/ENTRY

CORRECTION

Rev. 1.9

(07-17-08)

Rev. 1.9

(07-17-08)

All

Updated document references to Rev. C.

Section 13.1, "Maximum

Guaranteed Ratings*," on

page 105

Fixed commercial temp range to state “0°C to

+70°C for LAN91C111”

Rev. 1.9

(07-17-08)

Cover

Added bullet: “Commercial Temperature Range

from 0°C to 70°C (LAN91C111)”

Rev. 1.9

(07-17-08)

Section 8.24, "Bank 3 -

Revision Register," on

page 67

Changed REV default from “0001” to “0010”

Rev. 1.9

(07-17-08)

Table 14.3, “Asynchronous

Cycle - nADS=0,” on

page 112

Changed T1A time in table under figure from 10nS

min to 2nS min.

Rev. 1.9

(07-17-08)

Section 10.4, "Typical Flow

of Event For Receive," on

page 87

In step 4, changed last sentence from “If CRC is

incorrect the packet memory is released and no

interrupt will occur.”, to “The RCV_BAD bit of the

Bank 1 Control Register controls whether or not to

generate interrupts when bad CRC packets are

received.”

Rev. 1.9

(07-17-08)

Section 7.7.14, "Receive

Polarity Correction," on

page 40

Added note at end of 10 Mbps subsection stating

“The first 3 received packets must be discarded

after the correction of a reverse polarity condition.”

Revision 1.91 (08-18-08)

128

DATASHEET

SMSC LAN91C111 REV C

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