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LAN9210-ABZJ

Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

SMSC -> Microchip 

Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

1.11 Host Bus Interface (SRAM Interface)

The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as

an interface for the LAN9210 Control and Status Registers (CSR’s).

The host bus interface is the primary bus for connection to the embedded host system. This interface

models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.

Programmed I/O transactions are supported.

The LAN9210 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits

wide. The LAN9210 can be interfaced to either Big-Endian or Little-Endian processors and includes

mixed endian support for FIFO accesses.

SMSC LAN9210

13

DATASHEET

Revision 2.7 (03-15-10)

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