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LAN9217-MT

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support

SMSC -> Microchip 

NAME

General Purpose

I/O data,

nLED1 (Speed

Indicator),

nLED2 (Link &

Activity Indicator),

nLED3 (Full-

Duplex

Indicator).

RBIAS

Test Pin

Internal Regulator

Power

+3.3V I/O Power

I/O Ground

+3.3V Analog

Power

Analog Ground

Core Voltage

Decoupling

Core Ground

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support

Datasheet

Table 2.5 System and Power Signals (continued)

SYMBOL

BUFFER

TYPE

NUM

PINS

DESCRIPTION

GPIO[2:0]/

nLED[3:1]

RBIAS

ATEST

VREG

IS/O12/

OD12

AI

I

P

3

General Purpose I/O data: These three

general-purpose signals are fully programmable

as either push-pull output, open-drain output or

input by writing the GPIO_CFG configuration

register in the CSR’s. They are also multiplexed

as GP LED connections.

GPIO signals are Schmitt-triggered inputs.

When configured as LED outputs these signals

are open-drain.

nLED1 (Speed Indicator). This signal is driven

low when the operating speed is 100Mbs,

during auto-negotiation and when the cable is

disconnected. This signal is driven high only

during 10Mbs operation.

nLED2 (Link & Activity Indicator). This signal

is driven low (LED on) when the LAN9217

detects a valid link. This signal is pulsed high

(LED off) for 80mS whenever transmit or

receive activity is detected. This signal is then

driven low again for a minimum of 80mS, after

which time it will repeat the process if TX or RX

activity is detected. Effectively, LED2 is

activated solid for a link. When transmit or

receive activity is sensed LED2 will flash as an

activity indicator.

nLED3 (Full-Duplex Indicator). This signal is

driven low when the link is operating in full-

duplex mode.

1

PLL Bias: Connect to an external 12.0K ohm

1.0% resistor to ground. Used for the PLL Bias

circuit.

1

This pin must be connected to VDD for normal

operation.

1

3.3V input for internal voltage regulator

VDD_IO

GND_IO

P

8

+3.3V I/O logic power supply pins

P

8

Ground for I/O pins

VDD_A

P

3

+3.3V analog power supply pins. See Note 2.1.

VSS_A

P

4

Ground for analog circuitry

VDD_CORE

P

GND_CORE

P

2

+1.8 V from internal core regulator. Both pins

must be connected together externally. Each

pin requires a 0.01uF decoupling capacitor. In

addition, pin 3 requires a bulk 10uF capacitor

(<2 Ohm ESR) in parallel. These pins must not

be used to supply power to other external

devices. See Note 2.1.

2

Ground for internal digital logic

Revision 2.7 (03-15-10)

18

DATASHEET

SMSC LAN9217

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