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LAN9218I

High-Performance Single Chip 10/100 Ethernet Controller with HP Auto-MDIX & Industrial Temperature Support

SMSC -> Microchip 

High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX & Industrial Temperature Support

Datasheet

1.11 Host Bus Interface (SRAM Interface)

The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as

an interface for the LAN9218I Control and Status Registers (CSR’s).

The host bus interface is the primary bus for connection to the embedded host system. This interface

models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.

Programmed I/O transactions are supported.

The LAN9218I host bus interface supports 32-bit and 16-bit bus transfers; internally, all data paths are

32-bits wide. The LAN9218I can be interfaced to either Big-Endian or Little-Endian processors.

SMSC LAN9218I

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DATASHEET

Revision 1.5 (07-18-06)

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