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LAN8700I Datasheet PDF : 73 Pages
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM in a Small Footprint
Datasheet
Chapter 4 Architecture Details
4.1
Top Level Functional Architecture
Functionally, the PHY can be divided into the following sections:
„ 100Base-TX transmit and receive
„ 10Base-T transmit and receive
„ MII or RMII interface to the controller
„ Auto-negotiation to automatically determine the best speed and duplex possible
„ Management Control to read status registers and write control registers
MAC
TX_CLK
(for M II only)
Ext R ef_C LK (for R M II only)
M II 25 M hz by 4 bits
or
M II
R M II 50M hz by 2 bits
100M
PLL
25MHz
by 4 bits
4 B /5 B
Encoder
25M Hz by S cram bler
5 bits
and PISO
NRZI
C o n ve rte r
NRZI
125 M bps Serial
M LT-3
Converter MLT-3
Tx
D riv e r
MLT-3 M agnetics
M LT -3
RJ45
M LT -3
C A T -5
Figure 4.1 100Base-TX Data Path
4.2
4.2.1
4.2.2
100Base-TX Transmit
The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below.
100M Transmit Data Across the MII/RMII Interface
For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate
valid data. The data is latched by the PHY’s MII block on the rising edge of TX_CLK. The data is in
the form of 4-bit wide 25MHz data.
The MAC controller drives the transmit data onto the TXD bus and asserts TX_EN to indicate valid
data. The data is latched by the PHY’s MII block on the rising edge of REF_CLK. The data is in the
form of 2-bit wide 50MHz data.
4B/5B Encoding
The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from
4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 4.1. Each 4-bit data-nibble
is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for
control information or are not valid.
Revision 1.0 (02-09-07)
18
DATASHEET
SMSC LAN8700/LAN8700I

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