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LAN8710A-EZK-TR

MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology in a Small Footprint

SMSC -> Microchip 

MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology in a Small Footprint

Datasheet

Chapter 4 Architecture Details

4.1

Top Level Functional Architecture

Functionally, the transceiver can be divided into the following sections:

„ 100Base-TX transmit and receive

„ 10Base-T transmit and receive

„ MII or RMII interface to the controller

„ Auto-negotiation to automatically determine the best speed and duplex possible

„ Management Control to read status registers and write control registers

MAC

TX_CLK

(for MII only)

PLL

Ext Ref_CLK (for RMII only)

MII 25 Mhz by 4 bits

or

RMII 50Mhz by 2 bits

M II/R M II

25MHz

by 4 bits

4B/5B

Encoder

25MHz by

5 bits

S cra m b le r

and PISO

125 Mbps Serial

NRZI

C o n ve rte r

NRZI

M LT -3

C o n ve rte r

M LT -3

Tx

Driver

MLT-3 M agnetics MLT-3

RJ45

Figure 4.1 100Base-TX Data Path

M LT-3

CAT-5

4.2

4.2.1

100Base-TX Transmit

The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below.

100M Transmit Data Across the MII/RMII Interface

For MII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate

valid data. The data is latched by the transceiver’s MII block on the rising edge of TXCLK. The data

is in the form of 4-bit wide 25MHz data.

For RMII, the MAC controller drives the transmit data onto the TXD bus and asserts TXEN to indicate

valid data. The data is latched by the transceiver’s RMII block on the rising edge of REF_CLK. The

data is in the form of 2-bit wide 50MHz data.

SMSC LAN8710/LAN8710i

19

DATASHEET

Revision 1.0 (04-15-09)

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