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LAN8720A

Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

SMSC -> Microchip 

Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Datasheet

3.1.2

100BASE-TX Receive

The 100BASE-TX receive data path is shown in Figure 3.2. Each major block is explained in the

following subsections.

MAC

Ext Ref_CLK

PLL

RMII 50Mhz by 2 bits RMII

NRZI

NRZI MLT-3

Converter

Converter

25MHz

by 4 bits

4B/5B

Decoder

125 Mbps Serial

25MHz by

5 bits Descrambler

and SIPO

MLT-3

DSP: Timing

recovery, Equalizer

and BLW Correction

A/D

Converter

MLT-3 Magnetics

MLT-3

RJ45

MLT-3 CAT-5

3.1.2.1

3.1.2.2

6 bit Data

Figure 3.2 100BASE-TX Receive Data Path

100M Receive Input

The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio

transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second.

Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the

gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC

can be used.

Equalizer, Baseline Wander Correction and Clock and Data Recovery

The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates

for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,

and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m

and 150m.

If the DC content of the signal is such that the low-frequency components fall below the low frequency

pole of the isolation transformer, then the droop characteristics of the transformer will become

significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the

received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD

defined “killer packet” with no bit errors.

The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing

unit of the DSP, selects the optimum phase for sampling the data. This is used as the received

recovered clock. This clock is used to extract the serial data from the received signal.

Revision 1.4 (08-23-12)

20

DATASHEET

SMSC LAN8720A/LAN8720Ai

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