LC78845Q Ver la hoja de datos (PDF) - SANYO -> Panasonic

Número de pieza

componentes Descripción

Lista de partido

LC78845Q

Sample Rate Converter for Digital Audio

SANYO -> Panasonic 

LC78845Q

Pin Settings

1. Input master clock setup (when SPSEL is high)

Input the master clock for the internal digital filters to MCK1 (pin 3). Also, set whether that clock is 384fs or 512fs

with MKSEL (pin 1).

Pin

MKSEL

L

384fs

H

512fs

2. Input data fs setting (when SPSEL is high)

The input data sampling frequency must be set. FSEL1 and FSEL2 (pins 46 and 45) are used for this setting. Data

sampled at a 32 or 48 kHz sampling frequency is converted to data with a 44.1 kHz sampling frequency. If data

sampled at 44.1 kHz is input, it is passed through unchanged.

Sampling frequency

44.1 kHz

48 kHz

32 kHz

FSEL1

0

1

1

FSEL2

!

0

1

3. Output data setup

The output data can be switched between fs and 2fs. FSEL3 (pin 41) is used to change this setting.

Pin

L

H

FSEL3

fs

2fs

4. Setup from serial input

The MKSEL, FSEL1, FSEL2, MUTE, and STOP settings can be set using the serial bus by setting SPSEL (pin 11)

low. The 8 bits of input data is output in parallel regardless of the SPSEL setting.

Serial input format 1 (CCB = high)

Serial input format 2 (CCB = low)

No. 5236-8/10

Share Link: