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LH52258A

CMOS 32K × 8 Static RAM

Sharp Electronics 

LH52258A

CMOS 32K × 8 Static RAM

TIMING DIAGRAMS – READ CYCLE

Read Cycle No. 1

Chip is in Read Mode: W is HIGH, E is LOW and G is

LOW. Read cycle timing is referenced from when all

addresses are stable until the first address transition.

Crosshatched portion of Data Out implies that data lines

are in the Low-Z state but the data is not guaranteed to

be valid until tAA.

Read Cycle No. 2

Chip is in Read Mode: W is HIGH. Timing illustrated

for the case when addresses are valid before E goes

LOW. Data Out is not specified to be valid until tEA or tGA,

but may become valid as soon as tELZ or tGLZ. Outputs

will transition from High-Z to Valid Data Out. Valid data will

be present following tGA only if tEA timing is met.

ADDRESS

DQ

tRC

VALID ADDRESS

tAA

PREVIOUS DATA

tOH

VALID DATA

Figure 5. Read Cycle No. 1

52258A-5

E

G

DQ

SUPPLY

CURRENT

tRC

tEA

tGA

tGLZ

tELZ

tPU

tPD

tEHZ

tGHZ

VALID DATA

Figure 6. Read Cycle No. 2

52258A-6

6

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