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LH540215

512 × 18 / 1024 × 18 Synchronous FIFO

Sharp Electronics 

512 x 18/1024 x 18 Synchronous FIFO

DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d)

LH540215/25

WORD 0

17

3

PROGRAMMABLE-ALMOST-EMPTY-FLAG-OFFSET VALUE 1, 2

10 9

8

0

WORD 1

3

PROGRAMMABLE-ALMOST-FULL-FLAG-OFFSET VALUE 1, 2

17

10 9

8

0

WORD 2

Reserved for

future use.

CONTROL REGISTER 4, 5

6

5

4

32

17

12 11

7

6

5

43

2

CONTROL-REGISTER BITS:

6 Future use to control depth cascading and interlocked paralleling.

5 Enables suppressing reading whenever data outputs are disabled.

4 Makes PAF synchronous.

3 2 Makes HF synchronous. (See the Control-Register Format

table for the encoding of bits 02-03.)

1 Makes PAE synchronous.

0 Selects reinitialized addressing of the programmable registers.

See Table 5 for a

more complete

description of these

effects.

NOTES:

1. Default offset values are 6310 = 3F16 (LH540215) or 12710 = 7F16 (LH540225).

2. Bits 9-17 (LH540215) or bits 10-17 (LH540225) of both offset-value registers should

in all cases be programmed LOW (zero).

3. This bit position is used for offset values in the LH540225 only. In the LH540215, it

always should be programmed LOW.

4. See the Control-Register Format table for the default states of the Control Register,

for EMODE = HIGH (IDT-Compatible Operating Mode) and for EMODE = LOW (Enhanced Operating Mode).

The Control Register is not accessible or visible in IDT-Compatible Operating Mode.

5. The assertion of EMODE (LOW) forces Control Register bits 00-05 HIGH during a reset operation.

After that, these bits may be programmed at will.

= Reserved. Do not load with non-zero information.

BOLD ITALIC = Enhanced Operating Mode.

Figure 5. Programmable Registers

1

0

1

0

540215-4

The Control Register configuration is shown in Fig-

ure 5 and in Table 5. For the Control Register, in the

IDT-Compatible Operating Mode, with EMODE deas-

serted (HIGH), the default value for all Control-Register

bits is zero (LOW). In the Enhanced Operating Mode,

with EMODE asserted (LOW), the default value for

bits 00-05 is HIGH, and the default value for bits 06-11

is LOW.

Whenever LD and WEN are simultaneously being

asserted (are both LOW), the 18-bit data word from the

data inputs D0 – D17 is written into the Programmable-

BOLD ITALIC = Enhanced Operating Mode

Almost-Empty-Flag-Offset-Value Register at the first ris-

ing edge (LOW-to-HIGH transition) of the write clock

(WCLK). (See Table 3.) If LD and WEN continue to be

simultaneously asserted, another 18-bit data word from

the data inputs D0 – D17 is written into the Programma-

ble-Almost-Full-Flag-Offset-Value Register at the second

rising edge of WCLK.

What happens next is determined by the state of the

EMODE control input. If it is deasserted (HIGH), the next

18-bit word from the data inputs D0 – D17 is written back

into the Programmable-Almost-Empty-Flag-Offset-Value

Register again.

17

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