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LM3S801

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LM3S801 Data Sheet

Table of Contents

Legal Disclaimers and Trademark Information.............................................................................. 2

Revision History ............................................................................................................................. 18

About This Document..................................................................................................................... 19

Audience........................................................................................................................................................... 19

About This Manual............................................................................................................................................ 19

Related Documents .......................................................................................................................................... 19

Documentation Conventions............................................................................................................................. 19

1.

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.5

Architectural Overview ....................................................................................................... 22

Product Features ................................................................................................................................. 22

Target Applications .............................................................................................................................. 26

High-Level Block Diagram ................................................................................................................... 27

Functional Overview ............................................................................................................................ 28

ARM Cortex™-M3 ............................................................................................................................... 28

Motor Control Peripherals .................................................................................................................... 28

Analog Peripherals .............................................................................................................................. 29

Serial Communications Peripherals..................................................................................................... 29

System Peripherals.............................................................................................................................. 30

Memory Peripherals............................................................................................................................. 31

Additional Features .............................................................................................................................. 31

Hardware Details ................................................................................................................................. 32

System Block Diagram ........................................................................................................................ 33

2.

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core........................................................................................ 34

Block Diagram ..................................................................................................................................... 35

Functional Description ......................................................................................................................... 35

Serial Wire and JTAG Debug .............................................................................................................. 35

Embedded Trace Macrocell (ETM) ...................................................................................................... 36

Trace Port Interface Unit (TPIU) .......................................................................................................... 36

ROM Table .......................................................................................................................................... 36

Memory Protection Unit (MPU) ............................................................................................................ 36

Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 36

3. Memory Map ........................................................................................................................ 37

4. Interrupts ............................................................................................................................. 39

5.

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

JTAG Interface .................................................................................................................... 42

Block Diagram ..................................................................................................................................... 43

Functional Description ......................................................................................................................... 43

JTAG Interface Pins............................................................................................................................. 44

JTAG TAP Controller ........................................................................................................................... 45

Shift Registers ..................................................................................................................................... 46

Operational Considerations ................................................................................................................. 46

Initialization and Configuration............................................................................................................. 47

Register Descriptions........................................................................................................................... 48

Instruction Register (IR) ....................................................................................................................... 48

Data Registers ..................................................................................................................................... 50

6. System Control.................................................................................................................... 52

6.1 Functional Description ......................................................................................................................... 52

6.1.1 Device Identification............................................................................................................................. 52

October 8, 2006

3

Preliminary

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