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LMS12

12-bit Cascadable Multiplier-Summer

LOGIC Devices 

DEVICES INCORPORATED

LMS12

12-bit Cascadable Multiplier-Summer

FIGURE 1. FLOW DIAGRAM FOR 5-TAP FIR FILTER

x(n)

h4

h3

Z–1

h2

Z–1

h1

Z–1

h0

Z–1

y(n)

x(n)

A4

h4

A3

h3

A2

h2

A1

h1

A0

h0

Z–1

Z–1

Z–1

Z–1

Z–1

y(n)

APPLICATIONS

The LMS12 is designed specifically for

high-speed FIR filtering applications

requiring a throughput rate of one

output sample per clock period. By

cascading LMS12 units, the transpose

form of the FIR transfer function is

implemented directly, with each of the

LMS12 units supplying one of the

filter weights, and the cascaded

summers accumulating the results.

The signal flow graph for a 5-tap FIR

filter and the equivalent implementa-

tion using LMS12’s is shown in

Figure 1.

The operation of the 5-tap FIR filter

implementation of Figure 1 is depicted

in Table 1. The filter weights h4 - h0

are assumed to be latched in the B

input registers of the LMS12 units.

The x(n) data is applied in parallel to

the A input registers of all devices.

For descriptive purposes in the table,

the A register contents and sum

output data of each device is labelled

according to the index of the weight

applied by that device; i.e., S0 is

produced by the rightmost device,

which has h0 as its filter weight and

A0 as its input register contents. Each

column represents one clock cycle,

with the data passing a particular

point in the system illustrated across

each row.

Multiplier-Summers

2

08/16/2000–LDS.S12-J

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