LPC47M102 Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47M102

100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications

SMSC -> Microchip 

Indication of 32kHz Clock

There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M10x. This bit is located at

bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR

POR.

Bit[0] (CLK32_PRSN) is defined as follows:

0=32kHz clock is connected to the CLKI32 pin (default)

1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).

Bit 0 controls the source of the 32kHz (nominal) clock for the fan tachometer logic, the LED blink logic and the “wake

on specific key” logic. When the external 32kHz clock is connected, that will be the source for the fan tachometer,

LED and “wake on specific key” logic. When the external 32kHz clock is not connected, an internal 32kHz clock

source will be derived from the 14MHz clock for the fan tachometer, LED and “wake on specific key” logic.

The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not connected.

These functions will work under VCC power even if the external 32kHz clock is not connected.

• Wake on specific key

• LED blink

• Fan Tachometer

Trickle Power Functionality

When the LPC47M10x is running under VTR only (VCC removed), PME wakeup events are active and (if enabled)

able to assert the nIO_PME pin active low. The following lists the wakeup events:

• UART 1 Ring Indicator

• UART 2 Ring Indicator

• Keyboard data

• Mouse data

• Wake on Specific Key Logic

• Fan Tachometers (Note)

• GPIOs for wakeup. See below.

Note. The Fan Tachometers can generate a PME when VCC=0. Clear the enable bits for the fan tachometers

before removing fan power.

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.

ƒ I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may

only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.

ƒ I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by

VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present.

The GPIOs that are used for PME wakeup as input are GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41,

GP43, GP50-GP57, GP60, GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 -

see below):

• Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load

on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins

have input buffers into the wakeup logic that are powered by VTR.

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