LPC47M14E-NC Ver la hoja de datos (PDF) - SMSC -> Microchip
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LPC47M14E-NC
SMSC -> Microchip
LPC47M14E-NC Datasheet PDF : 205 Pages
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QFP
PIN #
32
33
34
35
36
37
38
39
41
42
43
45
46
47
50
48
49
17
28
NAME
TOTAL SYMBOL
BUFFER
TYPE
General Purpose I/O
/Joystick 1 Button 1
General Purpose I/O
/Joystick 1 Button 2
General Purpose I/O
/Joystick 2 Button 1
General Purpose I/O
/Joystick 2 Button 2
General Purpose I/O
/Joystick 1 X-Axis
General Purpose I/O
/Joystick 1 Y-Axis
General Purpose I/O
/Joystick 2 X-Axis
General Purpose I/O
/Joystick 2 Y-Axis
General Purpose I/O / P17
General Purpose I/O / P16
/nDS1
General Purpose I/O / P12
/nMTR1
General Purpose I/O /
System Option
General Purpose I/O
/MIDI_IN
General Purpose I/O
/MIDI_OUT
General Purpose I/O
/SMI Output
General Purpose I/O /
LED
General Purpose I/O /
LED
General Purpose I/O /
Power Management Event
General Purpose I/O
/Device Disable Reg.
Control
GENERAL PURPOSE I/O (19)
1
GP10 /J1B1 IS/O8
1
GP11 /J1B2 IS/O8
1
GP12 /J2B1 IS/O8
1
GP13 /J2B2 IS/O8
1
GP14 /J1X
IO12
1
GP15 /J1Y
IO12
1
GP16 /J2X
IO12
1
GP17 /J2Y
IO12
1
GP20 /P17
IO8
1
GP21 /P16/ IO12
nDS1
1
GP22 /P12/ IO12
nMTR1
1
GP24
IO8
/SYSOPT
1
GP25
IO8
/MIDI_IN
1
GP26
IO12
/MIDI_OUT
1 GP27
IO12
/nIO_SMI
1
GP60 /LED1 IO12
1
GP61 /LED2 IO12
1 GP42
/nIO_PME
IO12
1
GP43/DDRC IO8
BUFFER TYPE
PER FUNCTION
(NOTE 1)
(IS/O8/OD8)/IS
(IS/O8/OD8)/IS
(IS/O8/OD8)/IS
(IS/O8/OD8)/IS
(I/O12/OD12)/ IO12
(I/O12/OD12)/ IO12
(I/O12/OD12)/ IO12
(I/O12/OD12)/ IO12
(I/O8/OD8)/IO8
(I/O12/OD12)/
IO12/(O12/OD12)
(I/O12/OD12)/
IO12/(O12/OD12)
(I/O8/OD8)
(I/O8/OD8)/I
(I/O12/OD12)/O12
(I/O12/OD12)/ OD12
(I/O12/OD12)/O12
(I/O12/OD12)/O12
(I/O12/OD12)/ OD12
(I/O8/OD8)/I
NOTES
8
10
10
Note:
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
The "n" as the first letter of a signal name or the “#” as the suffix of a signal name indicates an "Active Low"
signal.
Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis
represent multiple buffer types for a single pin function.
The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal
follows the protocol defined for the LRESET# signal in the “Low Pin Count Interface Specification”.
For USB Hub functionality, the 32 KHz input clock must always be connected. There is a bit in the
configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is
connected. This bit determines the clock source for the fan tachometer, LED and “wake on specific key”
logic. This bit must always be set to ‘0’ (‘0’=32 KHz clock connected; reset default=‘0’).
The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and Hard Reset.
These pins revert to their non-inverting GPIO input function when VCC is removed from the part.
The IRTX pins (IRTX2/GP35 and GP53/TXD2 (IRTX)) are driven low when the part is powered by VTR
(VCC=0V with VTR=3.3V). These pins will remain low following a power-up (VCC POR) until serial port 2
is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the
Serial Port 2 block.
The VCC power-up default for this pin is Logic “0” if the IRTX function is programmed on the GPIO.
VTR must not be connected to VCC. The 32 KHz input clock must not be driven high whenVTR = 0v.
SMSC DS – LPC47M14X
Page 13
Rev. 03/19/2001
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