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LPC47M172-NR

Advanced I/O Controller with Motherboard GLUE Logic

SMSC -> Microchip 

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Figure 13.21 - Serial Port Data...................................................................................................................................216

Figure 13.22 - Keyboard/Mouse Receive/Send Data Timing .....................................................................................217

Figure 13.23 - Fan Tachometer Input Timing .............................................................................................................218

Figure 13.24 - Power Led Output Timing ...................................................................................................................218

Figure 13.25 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Up Before VCC5V/ V_5P0_STBY ...............219

Figure 13.26 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Up Before VCC/VTR ...............219

Figure 13.27 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Down Before VCC5V/ V_5P0_STBY...........220

Figure 13.28 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Down Before VCC/VTR...........220

Figure 13.29 - Rise, Fall and Propagation Timings ....................................................................................................221

Figure 13.30 - Reseme Reset Sequence ...................................................................................................................223

Figure 14.1 - 128 Pin MQFP Package Outline, 14x20x2.7 Body, 3.2mm Footprint....................................................224

Figure 15.1 - Example XOR Chain Circuitry...............................................................................................................225

List Of Tables

Table 3.1 - LPC47M172 Pin Description ......................................................................................................................15

Table 3.2 - Pins with Internal Resistors........................................................................................................................24

Table 3.3 - Pins that Require External Resistors..........................................................................................................24

Table 3.4 - Default State of Pins ..................................................................................................................................26

Table 6.1 - Super I/O Block Logical Device Number and Addresses ...........................................................................33

Table 6.2 - Status, Data and Control Registers............................................................................................................38

Table 6.3 - Internal 2 Drive Decode - Normal...............................................................................................................42

Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................43

Table 6.5 - Tape Select Bits .........................................................................................................................................43

Table 6.6 - Drive Type ID .............................................................................................................................................44

Table 6.7 - Precompensation Delays ...........................................................................................................................45

Table 6.8 - Data Rates .................................................................................................................................................45

Table 6.9 - DRVDEN Mapping .....................................................................................................................................46

Table 6.10 - Default Precompensation Delays .............................................................................................................46

Table 6.11 - FIFO Service Delay..................................................................................................................................47

Table 6.12 - Status Register 0 .....................................................................................................................................50

Table 6.13 - Status Register 1 .....................................................................................................................................50

Table 6.14 - Status Register 2 .....................................................................................................................................51

Table 6.15 - Status Register 3 .....................................................................................................................................51

Table 6.16 - Description of Command Symbols ...........................................................................................................55

Table 6.17 - Instruction Set ..........................................................................................................................................57

Table 6.18 - Sector Sizes .............................................................................................................................................63

Table 6.19 - Effects of MT and N Bits ..........................................................................................................................64

Table 6.20 - Skip Bit vs Read Data Command.............................................................................................................64

Table 6.21 - Skip Bit vs. Read Deleted Data Command ..............................................................................................65

Table 6.22 - Result Phase Table..................................................................................................................................65

Table 6.23 - Verify Command Result Phase Table ......................................................................................................67

Table 6.24 - Typical Values for Formatting ..................................................................................................................68

Table 6.25 - Interrupt Identification...............................................................................................................................70

Table 6.26 - Drive Control Delays (ms) ........................................................................................................................71

Table 6.27 - Effects of WGATE and GAP Bits .............................................................................................................74

Table 6.28 - Addressing the Serial Port .......................................................................................................................75

Table 6.29 - Interrupt Control Table .............................................................................................................................78

Table 6.30 - Baud Rates ..............................................................................................................................................85

Table 6.31 - Reset Function Table ...............................................................................................................................86

Table 32 - Register Summary for an Individual UART Channel ...................................................................................87

Table 7.1 - Parallel Port Connector ..............................................................................................................................92

Table 7.2 - EPP Pin Descriptions .................................................................................................................................97

Table 7.3 - ECP Pin Descriptions...............................................................................................................................100

Table 7.4 - ECP Register Definitions..........................................................................................................................101

Table 7.5 - Mode Descriptions ...................................................................................................................................101

Table 7.6 - Extended Control Register .......................................................................................................................106

Table 7.7 - Programming for Configuration Register B (Bits 5:3) ...............................................................................106

Table 7.8 - Programming for Configuration Register B (Bits 2:0) ...............................................................................106

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)

Page 9

DATASHEET

SMSC LPC47M172

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