LPC47M192-NW Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47M192-NW

LPC Super I/O with Hardware Monitoring Block

SMSC -> Microchip 

Note 4: The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal

follows the protocol defined for the LRESET# signal in the “Low Pin Count Interface Specification”.

Note 5: These pins are inputs to VCC and VTR powered logic.

Note 6: The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and PCI Reset.

Note 7: The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are driven low when the part is powered by VTR

(VCC=0V with VTR=3.3V). These pins will remain low following a power-up (VCC POR) until serial port 2

is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the

Serial Port 2 block.

Note 8: The VCC power-up default for this pin is Logic “0” if the IRTX function is programmed on the GPIO.

Note 9: These pins are inputs to VCC powered logic.

Note 10: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs

after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the system must

ensure that these pins are high. See Section “Pins That Require External Pullup Resistor”.

Note 11: The GP24 /SYSOPT pin requires an external pulldown resistor to put the base IO address for configuration

at 0x02E. An external pullup resistor is required to move the base IO address for configuration to 0x04E.

Note 12: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power.

4.1 Buffer Name Descriptions

Note: The buffer type values are specified at VCC=3.3V

I

IM

IANG

IS

IMOD3

IMO3

O6

O8

OD8

IO8

IS/O8

O12

OD12

IO12

OD14

OP14

IOP14

IOD16

PCI_IO

PCI_O

PCI_I

PCI_ICLK

Input TTL Compatible - Super I/O Block.

Input - Hardware Monitoring Block.

Analog Input, Hardware Monitoring Block.

Input with Schmitt Trigger.

Input/Output (Open Drain), 3mA sink.

Input/Output, 3mA sink, 3mA source.

Output, 6mA sink, 3mA source.

Output, 8mA sink, 4mA source.

Open Drain Output, 8mA sink.

Input/Output, 8mA sink, 4mA source.

Input with Schmitt Trigger/Output, 8mA sink, 4mA source.

Output, 12mA sink, 6mA source.

Open Drain Output, 12mA sink.

Input/Output, 12mA sink, 6mA source.

Open Drain Output, 14mA sink.

Output, 14mA sink, 14mA source.

Input/Output, 14mA sink, 14mA source. Backdrive protected.

Input/Output (Open Drain), 16mA sink.

Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1)

Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1)

Input. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1)

Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2)

Note 1: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2.

Note 2: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.

4.2 Pins That Require External Pullup Resistors

4.2.1 SUPER I/O PINS

The following pins require external pullup resistors:

ƒ KDAT

ƒ KCLK

ƒ MDAT

ƒ MCLK

ƒ GP36/KBDRST if KBDRST function is used

ƒ GP37/A20M if A20M function is used

ƒ GP20/P17 If P17 function is used as an Open Drain Output

SMSC DS – LPC47M192

Page 20

DATASHEET

Rev. 03/30/05

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