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LPC47M192-NC

LPC Super I/O with Hardware Monitoring Block

SMSC -> Microchip 

TABLE OF CONTENTS

1 GENERAL DESCRIPTION .................................................................................................................... 3

2 PIN LAYOUT ........................................................................................................................................ 10

3 PIN CONFIGURATION ........................................................................................................................ 11

4 DESCRIPTION OF PIN FUNCTIONS.................................................................................................. 12

4.1 BUFFER NAME DESCRIPTIONS........................................................................................................... 20

4.2 PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS.......................................................................... 20

4.2.1 Super I/O Pins ........................................................................................................................................20

4.2.2 Hardware Monitoring Block Pins.............................................................................................................21

5 BLOCK DIAGRAM............................................................................................................................... 22

6 POWER FUNCTIONALITY .................................................................................................................. 23

6.1 VCC/HVCC POWER ........................................................................................................................ 23

6.1.1 3 VOLT OPERATION / 5 VOLT TOLERANCE .......................................................................................23

6.2 VREF PIN........................................................................................................................................ 23

6.3 VTR SUPPORT................................................................................................................................. 23

6.3.1 Trickle Power Functionality .....................................................................................................................23

6.4 32.768 KHZ TRICKLE CLOCK INPUT................................................................................................... 25

6.4.1 Indication of 32KHZ Clock ......................................................................................................................25

6.5 INTERNAL PWRGOOD..................................................................................................................... 25

6.6 MAXIMUM CURRENT VALUES............................................................................................................. 25

6.6.1 Super I/O Functions................................................................................................................................25

6.6.2 Hardware Monitoring Block Functions ....................................................................................................26

6.7 POWER MANAGEMENT EVENTS (PME/SCI)....................................................................................... 26

7 FUNCTIONAL DESCRIPTION............................................................................................................. 27

7.1 SUPER I/O REGISTERS ..................................................................................................................... 27

7.2 HOST PROCESSOR INTERFACE (LPC) ............................................................................................... 27

7.3 LPC INTERFACE ...............................................................................................................................28

7.3.1 LPC Interface Signal Definition...............................................................................................................28

7.3.2 LPC Cycles .............................................................................................................................................28

7.3.3 Field Definitions ......................................................................................................................................28

7.3.4 LFRAME# Usage....................................................................................................................................28

7.3.5 I/O Read and Write Cycles .....................................................................................................................29

7.3.6 DMA Read and Write Cycles ..................................................................................................................29

7.3.7 DMA Protocol .........................................................................................................................................29

7.3.8 POWER MANAGEMENT .......................................................................................................................29

7.3.8.1 CLOCKRUN Protocol .................................................................................................................................... 29

7.3.8.2 LPCPD Protocol.............................................................................................................................................. 29

7.3.9 SYNC Protocol .......................................................................................................................................29

7.3.9.1 Typical Usage ................................................................................................................................................. 29

7.3.9.2 SYNC Timeout ............................................................................................................................................... 30

7.3.9.3 SYNC Patterns and Maximum Number of SYNCS ........................................................................................ 30

7.3.9.4 SYNC Error Indication.................................................................................................................................... 30

7.3.9.5 I/O and DMA START Fields .......................................................................................................................... 30

7.3.9.6 Reset Policy..................................................................................................................................................... 30

7.3.10 LPC TRANSFERS ..............................................................................................................................30

7.3.10.1 Wait State Requirements................................................................................................................................. 30

7.4 FLOPPY DISK CONTROLLER .............................................................................................................. 31

7.4.1 FDC Internal Registers ...........................................................................................................................31

7.4.2 STATUS REGISTER ENCODING ..........................................................................................................41

7.4.3 Instruction Set.........................................................................................................................................48

7.4.4 DATA TRANSFER COMMANDS............................................................................................................54

7.4.5 DIRECT SUPPORT FOR TWO FLOPPY DRIVES.................................................................................64

SMSC DS – LPC47M192

Page 4

Rev. 03/30/05

DATASHEET

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