LPC47N267-MN(2000) Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47N267-MN
(Rev.:2000)

100 Pin LPC Notebook I/O with X-Bus Interface

SMSC -> Microchip 

STQFP PIN #

13

14

15

16

84

85

86

97

87

98

88

99

89

100

NAME

SYMBOL

BUFFER

TYPE PER

FUNCTION1

DESCRIPTION

Index

nINDEX

IS

This active low Schmitt Trigger input senses from

the disk drive that the head is positioned over the

beginning of a track, as marked by an index hole.

Track 0

nTRK0

IS

This active low Schmitt Trigger input senses from

the disk drive that the head is positioned over the

outermost track.

Write

Protected

nWRTPRT

IS

This active low Schmitt Trigger input senses from

the disk drive that a disk is write protected. Any

write command is ignored. The nWRPRT bit also

depends upon the state of the Force Write Protect

bit in the Force FDD Status Change configuration

register (see subsection CR17 in the

Configuration section).

Read Disk

Data

nRDATA

IS

Raw serial bit stream from the disk drive, low

active. Each falling edge represents a flux

transition of the encoded data.

SERIAL PORTS INTERFACE (16)

Receive Data RXD1

1

IS

Receiver serial data input for port 1.

Transmit

TXD1

O12

Transmit serial data output for port 1.

Data 1

Data Set

Ready 1

nDSR1

Data Set

Ready 2

nDSR2

I

Active low Data Set Ready inputs for the serial

port. Handshake signal which notifies the UART

that the modem is ready to establish the

communication link. The CPU can monitor the

status of nDSR signal by reading bit 5 of Modem

I

Status Register (MSR). A nDSR signal state

change from low to high after the last MSR read

will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable

Register is set, the interrupt is generated when

nDSR changes state.

Note: Bit 5 of MSR is the complement of nDSR.

Request to

Send 1

nRTS1

Request to nRTS2

Send 2

O6

Active low Request to Send outputs for the Serial

Port. Handshake output signal notifies modem that

the UART is ready to transmit data. This signal

O6

can be programmed by writing to bit 1 of the

Modem Control Register (MCR). The hardware

reset will reset the nRTS signal to inactive mode

(high). nRTS is forced inactive during loop mode

operation.

Clear to

Send 1

nCTS1

Clear to

Send 2

nCTS2

I

Active low Clear to Send inputs for the serial port.

Handshake signal which notifies the UART that the

modem is ready to receive data. The CPU can

monitor the status of nCTS signal by reading bit 4

of Modem Status Register (MSR). A nCTS signal

state change from low to high after the last MSR

I

read will set MSR bit 0 to a 1. If bit 3 of the

Interrupt Enable Register is set, the interrupt is

generated when nCTS changes state. The nCTS

signal has no effect on the transmitter.

Note: Bit 4 of MSR is the complement of nCTS.

Data Terminal nDTR1

Ready 1

Data Terminal nDTR2

Ready 2

O6

Active low Data Terminal Ready outputs for the

serial port. Handshake output signal notifies

modem that the UART is ready to establish data

communication link. This signal can be

O6

programmed by writing to bit 0 of Modem Control

Register (MCR). The hardware reset will reset the

nDTR signal to inactive mode (high). nDTR is

forced inactive during loop mode operation.

SMSC DS – LPC47N267

Page 9

Rev. 10/23/2000

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