LTC1287BCJ Ver la hoja de datos (PDF) - Linear Technology
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LTC1287BCJ Datasheet PDF : 16 Pages
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LTC1287
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Clock Rate vs Source
Resistance
500
VCC = 3V
VREF = 2.5V
400
CLK = 500kHz
300
200
+VIN +IN
100 RSOURCE–
–IN
Minimum Clock Rate for 0.1LSB
Error**
VCC = 3V
0.25
0.20
0.15
0.10
0.05
Maximum Filter Resistor vs Cycle
Time
10k
RFILTER
VIN
+
1k
CFILTER ≥1µF
–
100
10
0
100
1k
10k
RSOURCE– (Ω)
100k
LTC G10
1
–50 –25 0 25 50 75 100
10
AMBIENT TEMPERATURE (°C)
LTC1287 G11
100
1000
CYCLE TIME (µs)
10000
LTC1287 G12
Sample-and-Hold Acquisition
Time vs Source Resistance
100
VREF = 2.5V
VCC = 3V
TA = 25°C
0V TO 2.5V INPUT STEP
10
+ RSOURCE+
VIN
–
1
100
1k
10k
RSOURCE+ (Ω)
LTC1287 G13
Input Channel Leakage Current vs
Temperature
1000
900
GUARANTEED
800
700
600
500
400
300
200
ON CHANNEL
100
OFF CHANNEL
0
–50 –30 –10 10 30 50 70 90 110 130
AMBIENT TEMPERATURE (°C)
LTC1287 G14
Noise Error vs Reference Voltage
1.0
0.9 LTC1287 NOISE = 200µVP-P
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 0.5 1.0 1.5 2.0 2.5 3.0
REFERENCE VOLTAGE (V)
LTC1287 G15
* MAXIMUM CLK FREQUENCY REPRESENTS THE CLK FREQUENCY AT WHICH A 0.1LSB
SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST
DETECTED.
** AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY
(∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY
CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED.
*** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB
CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST
DETECTED.
PI FU CTIO S
# PIN
FUNCTION
DESCRIPTION
1
CS
Chip Select Input A logic low on this input enables the LTC1287.
2, 3 +IN, –IN Analog Inputs
These inputs must be free of noise with respect to GND.
4
GND
Analog Ground
GND should be tied directly to an analog ground plane.
5
VREF
6
DOUT
7
CLK
Reference Input
Digital Data Output
Shift Clock
The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND.
The A/D conversion result is shifted out of this output.
This clock synchronizes the serial data transfer.
8
VCC
Positive Supply
This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
5
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