1418CG Ver la hoja de datos (PDF) - Linear Technology
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1418CG Datasheet PDF : 30 Pages
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LTC1418
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
fSAMPLE(MAX)
tCONV
tACQ
tACQ + tCONV
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
fSCLK
fEXTCLKIN
tdEXTCLKIN
tH SCLK
tL SCLK
tH EXTCLKIN
tL EXTCLKIN
PARAMETER
CONDITIONS
MIN
TYP
MAX
Maximum Sampling Frequency
l 200
Conversion Time
l
3.4
4
Acquisition Time
l
0.3
1
Acquisition Plus Conversion Time
l
3.7
5
CS to RD Setup Time
(Notes 9, 10)
l
0
CS↓ to CONVST↓ Setup Time
(Notes 9, 10)
l 40
CS↓ to SHDN↓ Setup Time to Ensure Nap Mode
(Notes 9, 10)
l 40
SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode
(Note 10)
500
CONVST Low Time
(Notes 10, 11)
l 40
CONVST to BUSY Delay
Data Ready Before BUSY↑
CL = 25pF
l
35
70
20
35
l 15
Delay Between Conversions
(Note 10)
l 500
Wait Time RD↓ After BUSY↑
l –5
Data Access Time After RD↓
CL = 25pF
l
15
30
40
CL = 100pF
l
20
40
55
Bus Relinquish Time
8
20
Commercial
l
25
Industrial
l
30
RD Low Time
CONVST High Time
l
t10
40
Delay Time, SCLK↓ to DOUT Valid
Time from Previous Data Remain Valid After SCLK↓
Shift Clock Frequency
CL = 25pF (Note 9) l
CL = 25pF (Note 9) l 15
(Notes 9, 10)
0
35
70
25
12.5
External Conversion Clock Frequency
(Notes 9, 10)
0.03
4.5
Delay Time, CONVST↓ to External Conversion Clock Input (Notes 9, 10)
533
SCLK High Time
(Notes 9, 10)
10
SCLK Low Time
(Notes 9, 10)
20
EXTCLKIN High Time
(Notes 9, 10)
250
EXTCLKIN Low Time
(Notes 9, 10)
250
UNITS
kHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
µs
ns
ns
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VCC without latchup.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = 0V or –5V, fSAMPLE = 200kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when the
output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1µs after the conversion starts or after BUSY rises.
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.
1418fa
For more information www.linear.com/LTC1418
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