LTC1669IMS8-PBF Ver la hoja de datos (PDF) - Linear Technology

Número de pieza

componentes Descripción

Lista de partido

LTC1669IMS8-PBF

10-Bit Rail-to-Rail Micropower DAC with I2C Interface

Linear Technology 

LTC1669

APPLICATIONS INFORMATION

Write Word Protocol Used by the LTC1669

1

7

11

8

1

8

1

S Slave Address Wr A Command Byte A LSData Byte A

S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition

8

MSData Byte

11

AP

1669 TA03

Serial Digital Interface

The LTC1669 communicates with a host (master) using

the standard 2-wire interface. The Timing Diagram shows

the timing relationship of the signals on the bus. The two

bus lines, SDA and SCL, must be high when the bus is

not in use. External pull-up resistors or current sources,

such as the LTC1694 SMBus/I2C Accelerator, are required

on these lines.

The LTC1669 is a receive-only (slave) device. The master

can communicate with the LTC1669 using the Quick Com-

mand, Send Byte or Write Word protocols as explained

later.

The START and STOP Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

A START condition is generated by transitioning SDA

from high to low while SCL is high.

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

another I2C device.

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byte of information was received. The Acknowledge related

clock pulse is generated by the master. The master releases

the SDA line (HIGH) during the Acknowledge clock pulse.

The slave-receiver must pull down the SDA line during the

Acknowledge clock pulse so that it remains a stable LOW

during the HIGH period of this clock pulse.

Write Word Protocol

The master initiates communication with the LTC1669 with

a START condition and a 7-bit address followed by the Write

Bit (Wr) = 0. The LTC1669 acknowledges and the master

delivers the command byte. The LTC1669 acknowledges

and latches the command byte into the command byte

input register. The master then delivers the least significant

data byte. Again the LTC1669 acknowledges and the data

is latched into the least significant data byte input register.

The master then delivers the most significant data byte.

The LTC1669 acknowledges once more and latches the

data into the most significant data byte input register.

Lastly, the master terminates the communication with a

STOP condition. On the reception of the STOP condition,

the LTC1669 transfers the input register information to

output registers and the DAC output is updated.

Slave Address (MSOP Package Only)

The LTC1669 can respond to one of eight 7-bit addresses.

The first 4 bits (MSBs) have been factory programmed to

0100. The first 4 bits of the LTC1669-8 have been factory

programmed to 0011. The three address bits, AD2, AD1

and AD0 are programmed by the user and determine the

LSBs of the slave address, as shown in the table below:

LTC1669

LTC-1669-8

AD2

AD1

AD0

0100 xxx

0011 xxx

L

L

L

0100 000

0011 000

L

L

H

0100 001

0011 001

L

H

L

0100 010

0011 010

L

H

H

0100 011

0011 011

H

L

L

0100 100

0011 100

H

L

H

0100 101

0011 101

H

H

L

0100 110

0011 110

H

H

H

0100 111

0011 111

1669fa

9

Share Link: