1840 Ver la hoja de datos (PDF) - Linear Technology
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1840 Datasheet PDF : 12 Pages
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U
OPERATIO
Typical 2-Wire Serial I2C or SMBus Transmission
LTC1840
SDA
SCL
S
START
CONDITION
1-7
ADDRESS
8
9
R/W
ACK
1-7
8
9
DATA
ACK
1-7
8
DATA
9
P
STOP
ACK
CONDITION 1840 TD02
Serial Interface
• Simple 2-wire interface
• Multiple devices on same bus
• Idle bus must have SDA and SCL lines high
• LTC1840 is read/write
• Master controls bus
• Devices listen for unique address that precedes data
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. An acknowledge (LOW active)
generated by the slave lets the master know that the latest
byte of information was received. The acknowledge-
related clock pulse is generated by the master. The trans-
mitter master releases the SDA line (HIGH) during the
acknowledge clock pulse. The slave receiver must pull
down the SDA line during the acknowledge clock pulse so
that it remains stable LOW during the HIGH period of this
clock pulse.
When a slave receiver doesn’t acknowledge the slave
address (for example, it’s unable to receive because it’s
performing some real-time function), the data line must be
left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer.
If a slave receiver acknowledges the slave address, but
some time later in the transfer cannot receive any more
data bytes, the master must again abort the transfer. This
is indicated by the slave generating the “not acknowledge”
on the first byte to follow. The slave leaves the data line
HIGH and the master generates the STOP condition.
Commands Supported
The LTC1840 supports read byte, write byte, read word
(the second data byte will be all ones) and write word (the
second data byte will be ignored) commands.
Data Transfer Timing for Write Commands
In order to help assure that bad data is not written into the
LTC1840, data from a write command is only stored after
a valid acknowledge has been performed. The part will
detect that SDA is low on the rising edge of SCL that marks
the end of the period in which the LTC1840 acknowledges
the data write and then latch the data during the following
SCL low period.
LTC1840 Write Byte Protocol
1
7
11
8
1
8
11
START 1 1 1 B4 B3 B2 B1 WR ACK X X X X X R2 R1 R0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP
SLAVE
S
REGISTER
S
ADDRESS
00
ADDRESS
0
DATA
S
BYTE
0
LTC1840 Read Byte Protocol
1
7
11
8
11
7
11
8
11
START 1 1 1 B4 B3 B2 B1 WR ACK X X X X X R2 R1 R0 ACK START 1 1 1 B4 B3 B2 B1 RD ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP
SLAVE
ADDRESS
S
00
REGISTER
S
ADDRESS
0
SLAVE
S
DATA
ADDRESS
10
BYTE
M
1
1840 TD03
1840f
7
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