LTC1863CGN Ver la hoja de datos (PDF) - Linear Technology
Número de pieza
componentes Descripción
Lista de partido
LTC1863CGN Datasheet PDF : 18 Pages
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TIMING DIAGRAMS
t1 (For Short Pulse Mode)
t1
CS/CONV
50%
50%
CS/CONV
t4 (SDO Valid After CONV↓)
t4
0.4V
Hi-Z
SDO
2.4V
0.4V
t7 (SLEEP Mode Wake-Up Time)
t7
SCK
50%
SLEEP BIT (SLP = 0)
READ-IN
CS/CONV
50%
LTC1863/LTC1867
t2 (SDO Valid Before SCK↑),
t3 (SDO Valid Hold Time After SCK↓)
t2
SCK
0.4V
t3
SDO
2.4V
0.4V
t5 (SDI Setup Time Before SCK↑),
t6 (SDI Hold Time After SCK↑)
t5
t6
SCK
2.4V
SDI
CS/CONV
2.4V
2.4V
0.4V
0.4V
t8 (BUS Relinquish Time)
t8
2.4V
SDO
90%
10%
Hi-Z
1867 TD
APPLICATIONS INFORMATION
Overview
The LTC1863/LTC1867 are complete, low power multi-
plexed ADCs. They consist of a 12-/16-bit, 200ksps capaci-
tive successive approximation A/D converter, a precision
internal reference, a configurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 1.5µs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most significant bit (MSB) to the least significant bit
(LSB). The input is successively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low-power, differential
comparator. At the end of a conversion, the DAC output
balances the analog input. The SAR contents (a 12-/16-bit
data word) that represent the analog input are loaded into
the 12-/16-bit output latches.
18637fc
For more information www.linear.com/LTC1863
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