LTC1863CGN Ver la hoja de datos (PDF) - Linear Technology
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LTC1863CGN Datasheet PDF : 18 Pages
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LTC1863/LTC1867
APPLICATIONS INFORMATION
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
Internal Reference
The LTC1863/LTC1867 has an on-chip, temperature
compensated, curvature corrected, bandgap reference
that is factory trimmed to 2.5V. It is internally connected
to a reference amplifier and is available at VREF (Pin 10).
A 6k resistor is in series with the output so that it can be
easily overdriven by an external reference if better drift
and/or accuracy are required as shown in Figure 4. The
reference amplifier gains the VREF voltage by 1.638V/V
to 4.096V at REFCOMP (Pin 9). This reference amplifier
compensation pin, REFCOMP, must be bypassed with a
10µF ceramic or tantalum in parallel with a 0.1µF ceramic
for best noise performance.
10 VREF
2.5V
2.2µF
4.096V
9 REFCOMP
R1
6k BANDGAP
REFERENCE
REFERENCE
AMP
10µF
R2
15 GND
R3
LTC1863/LTC1867
1867 F04a
Figure 4a. LTC1867 Reference Circuit
5V
VIN
LT1019A-2.5
VOUT
+
10µF
10
2.2µF
9
VREF
LTC1863/
LTC1867
REFCOMP
0.1µF
15
GND
1867 F04b
Figure 4b. Using the LT1019-2.5 as an External Reference
Digital Interface
The LTC1863/LTC1867 have a very simple digital interface
that is enabled by the control input, CS/CONV. A logic rising
edge applied to the CS/CONV input will initiate a conversion.
After the conversion, taking CS/CONV low will enable the
serial port and the ADC will present digital data in two’s
complement format in bipolar mode or straight binary
format in unipolar mode, through the SCK/SDO serial port.
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 3µs and a maximum conversion time,
3.5µs, over the full operating temperature range. The typi-
cal acquisition time is 1.1µs, and a throughput sampling
rate of 200ksps is tested and guaranteed.
Automatic Nap Mode
The LTC1863/LTC1867 go into automatic nap mode when
CS/CONV is held high after the conversion is complete
(see Figure 6). With a typical operating current of 1.3mA
and automatic 150µA nap mode between conversions, the
power dissipation drops with reduced sample rate. The
ADC only keeps the VREF and REFCOMP voltages active
when the part is in the automatic nap mode. The slower the
sample rate allows the power dissipation to be lower (see
Figure 5).
2.0
VDD = 5V
1.5
1.0
0.5
0
1
10
100
1000
fSAMPLE (ksps)
18637 G10
Figure 5. Supply Current vs fSAMPLE
For more information www.linear.com/LTC1863
18637fc
13
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