LTC1867CGN Ver la hoja de datos (PDF) - Linear Technology
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LTC1867CGN Datasheet PDF : 18 Pages
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LTC1863/LTC1867
PIN FUNCTIONS
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog
inputs must be free of noise with respect to GND. CH7/
COM can be either a separate channel or the common
minus input for the other channels.
REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass
to GND with 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor (4.096V Nominal). To overdrive
REFCOMP, tie VREF to GND.
VREF (Pin 10): 2.5V Reference Output. This pin can also
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with 2.2µF tantalum
capacitor in parallel with 0.1µF ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.
SCK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
SDO (Pin 13): Digital Data Output. The A/D conversion
result is shifted out of this output. Straight binary format
for unipolar mode and two’s complement format for
bipolar mode.
SDI (Pin 14): Digital Data Input Pin. The A/D configuration
word is shifted into this input.
GND (Pin 15): Analog and Digital GND.
VDD (Pin 16): Analog and Digital Power Supply. Bypass to
GND with 10µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor.
TYPICAL CONNECTION DIAGRAM
±2.048V +
DIFFERENTIAL
INPUTS –
4.096V
SINGLE-ENDED
+
INPUT
CH0
VDD
CH1
GND
CH2
SDI
CH3
LTC1863/
LTC1867
SDO
CH4
SCK
CH5
CS/CONV
CH6
VREF
CH7/COM REFCOMP
5V
DIGITAL
I/O
4.096V
10µF
2.5V
2.2µF
18637 TCD
TEST CIRCUITS
Load Circuits for Access Timing
5V
DN
3k
CL
3k
DN
CL
Load Circuits for Output Float Delay
5V
DN
3k
CL
3k
DN
CL
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
18637 TC01
(A) VOH TO Hi-Z
8
For more information www.linear.com/LTC1863
(B) VOL TO Hi-Z
18637 TC02
18637fc
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