LTC2265IUJ-12-PBF(RevB) Ver la hoja de datos (PDF) - Linear Technology

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LTC2265IUJ-12-PBF
(Rev.:RevB)

12-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs

Linear Technology 

LTC2265-12/

LTC2264-12/LTC2263-12

TIMING DIAGRAMS

2-Lane Output Mode, 12-Bit Serialization

ANALOG

INPUT

ENC–

ENC+

tAP

N

tENCH

N+1

tENCL

DCO–

DCO+

FR+

tFRAME

tDATA

FR–

OUT#A–

OUT#A+

OUT#B–

OUT#B+

tPD

tSER

D7 D5 D3 D1 D11 D9 D7 D5 D3

D6 D4 D2 D0 D10 D8 D6 D4 D2

SAMPLE N-6

SAMPLE N-5

tSER

tSER

D1 D11 D9 D7

D0 D10 D8 D6

SAMPLE N-4

226512 TD03

1-Lane Output Mode, 16-Bit Serialization

ANALOG

INPUT

ENC–

tAP

N

tENCH

tENCL

N+1

ENC+

DCO–

tSER

DCO+

FR–

tFRAME

tDATA

tSER

FR+

OUT#A–

OUT#A+

tPD

tSER

DX* DY* 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* 0

SAMPLE N-6

SAMPLE N-5

OUT#B+, OUT#B– ARE DISABLED

*DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT

VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO

LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.

0 D11 D10 D9 D8

SAMPLE N-4

226512 TD04

22654312fb

9

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