LTC2264IUJ-12-TRPBF Ver la hoja de datos (PDF) - Linear Technology
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LTC2264IUJ-12-TRPBF Datasheet PDF : 32 Pages
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LTC2265-12/
LTC2264-12/LTC2263-12
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2265-12
LTC2264-12
LTC2263-12
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD
Analog Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
OVDD Output Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
IVDD
Analog Supply Current Sine Wave Input
l
82 98
52 63
42 50
mA
IOVDD
Digital Supply Current 1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode l
2-Lane Mode, 3.5mA Mode l
11
20
15 18
28 31
10
19
15 18
28 31
10
mA
18
mA
14 17
mA
27 31
mA
PDISS Power Dissipation
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode l
2-Lane Mode, 3.5mA Mode l
167
184
175 209
198 232
112
128
121 146
144 169
94
mW
108
mW
101 121 mW
124 146 mW
PSLEEP
PNAP
Sleep Mode Power
Nap Mode Power
1
1
1
mW
60
60
60
mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
20
20
20
mW
(No Increase for Sleep Mode)
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2265-12
LTC2264-12
LTC2263-12
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS
Sampling Frequency (Notes 10, 11)
l5
65 5
45 5
25 MHz
tENCL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100
ns
Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100
ns
tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 100 11.88 12.5 100 19 20 100
ns
Duty Cycle Stabilizer On l 2 7.69 100 2 12.5 100 2 20 100
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
6
22654312f
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