LTC2264UJ-14(RevB) Ver la hoja de datos (PDF) - Linear Technology

Número de pieza

componentes Descripción

Lista de partido

LTC2264UJ-14
(Rev.:RevB)

14-Bit, 65Msps/40Msps/25Msps Low Power Dual ADCs

Linear Technology 

LTC2265-14/

LTC2264-14/LTC2263-14

CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 5)

LTC2265-14

LTC2264-14

LTC2263-14

PARAMETER

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

Resolution (No Missing Codes)

l 14

14

14

Bits

Integral Linearity Error

Differential Analog Input (Note 6) l –3 ±1 3 –3 ±1 3 –3 ±1 3

LSB

Differential Linearity Error

Differential Analog Input

l –0.8 ±0.3 0.8 –0.8 ±0.3 0.8 –0.8 ±0.3 0.8

LSB

Offset Error

(Note 7)

l –12 ±3 12 –12 ±3 12 –12 ±3 12

mV

Gain Error

Internal Reference

External Reference

–0.8

–0.8

–0.8

%FS

l –2.1 –0.8 0.5 –2.1 –0.8 0.5 –2.1 –0.8 0.5

%FS

Offset Drift

±20

±20

±20

µV/°C

Full-Scale Drift

Internal Reference

External Reference

±30

±30

±30

ppm/°C

±10

±10

±10

ppm/°C

Gain Matching

External Reference

±0.2

±0.2

±0.2

%FS

Offset Matching

±3

±3

±3

mV

Transition Noise

External Reference

1.2

1.2

1.2

LSBRMS

ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VIN

VIN(CM)

VSENSE

Analog Input Range (AIN+ – AIN–)

Analog Input Common Mode (AIN+ + AIN–)/2

External Voltage Reference Applied to SENSE

1.7V < VDD < 1.9V

l

1 to 2

VP-P

Differential Analog Input (Note 8) l VCM – 100mV VCM VCM + 100mV

V

External Reference Mode

l 0.625

1.250

1.300

V

IINCM Analog Input Common Mode Current

Per Pin, 65Msps

Per Pin, 40Msps

Per Pin, 25Msps

81

µA

50

µA

31

µA

IIN1

Analog Input Leakage Current (No Encode)

0 < AIN+, AIN– < VDD

l

–1

1

µA

IIN2

PAR/SER Input Leakage Current

0 < PAR/SER < VDD

l

–3

3

µA

IIN3

tAP

tJITTER

CMRR

SENSE Input Leakage Current

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Jitter

Analog Input Common Mode Rejection Ratio

0.625 < SENSE < 1.3V

l

–6

0

0.15

80

6

µA

ns

psRMS

dB

BW-3B Full-Power Bandwidth

Figure 6 Test Circuit

800

MHz

22654314fb

3

Share Link: