TIMING DIAGRAMS
UVLO
PDT
INT
EN
(LTC2953-1)
PB
UVLO
IGNORED
tDB, OFF
16 CYCLES
tPD, Min
tPDT
tINT, Max
PB IGNORED
Figure 5. UVLO Power Down Timing: UVLO Low for t > (tPD, Min + tPDT)
LTC2953
2953 TD05
0.5V 0.5V
VM
tUV
tRST
RST
2953 TD06
Figure 6. Voltage Monitor Reset Timing
0.5V
PFI
0.504V
tPFI
tPFI
PFO
2953 TD07
Figure 7. Power Fail Comparator Timing
tKILL(PW)
0.6V
0.63V
KILL
EN
(LTC2953-1)
tKILL(PD)
2953 TD08
Figure 8. ⎯K⎯I⎯L⎯L Minimum Pulse Width and Propagation Delay
2953f
11