LV766106F Ver la hoja de datos (PDF) - SANYO -> Panasonic
Número de pieza
componentes Descripción
Lista de partido
LV766106F Datasheet PDF : 41 Pages
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LV766106F
Parameter
Symbol
[VIFblock ]
Maximum RF AGC VRFH
voltage
Minimum RF AGC VRFL
voltage
RF AGC Delay Pt RFAGC0
(@DAC=0)
RF AGC Delay Pt RFAGC63
(@DAC=63)
Input sensitivity Vi
Sync tip level
Video output
amplitude
VOtip
VO
Video S/N
S/N
C-S beat level
IC-S
Differential gain DG
Differential phase DP
APC pull-in range fPU, fPL
(U),(L)
NT Trap1
(4.5MHz)
BG Trap 1
(5.5MHz)
I Trap1
(6.0MHz)
DK Trap1
(6.5MHz)
NTR1
BTR1
ITR1
DTR1
Test point Input signal
Test method
Bus conditions
58
SG1
80dBμ
SG1
58 80dBμ
SG1
58
58 SG1
SG6
61
61
SG1
80dBμ
SG6
61 80dBμ
SG1
61 80dBμ
SG1
SG2
61 SG3
61
SG5
80dBμ
61
SG5
80dBμ
SG4
61 80dBμ
61 SG7
SG7
61
61 SG7
61 SG7
Measure the DC voltage at pin 58.
RF.AGC=”000000”
Measure the DC voltage at pin 58.
RF.AGC=”111111”
Obtain the input level at which the DC voltage at pin 58 becomes RF.AGC=”000000”
2.5V.
Obtain the input level at which the DC voltage at pin 58 becomes RF.AGC=”111111”
2.5V.
Using an oscilloscope, observe the level at pin 61 and obtain the
input level at which the waveform's amplitude becomes 1.4Vp-p.
Measure the DC voltage at pin 61.
Using an oscilloscope, adjust the waveform's amplitude at pin 61 to
about 2Vpp and measure the waveform’s amplitude.
* After this measurement, set "Video Level DAC" to the value
adjusted .
Measure the noise voltage (Vsn) at pin 61 with an RMS voltmeter
through a 10kHz to 5.0MHz band-pass filter and calculate
20log(1.43/Vsn).
Input a 80dBμ SG1 signal and measure the DC voltage (V60) at pin
60. Mix SG1=74dBμ, SG2=64dBμ, and SG3=64dBμ to enter the
mixture in the VIF IN. Apply V60 to pin 60 from an external DC
power supply. Using a spectrum analyzer, measure the difference
between pin 61’s 4.43MHz component and 1.07MHz component.
Using a vector scope, measure the level at Pin 61.
Using a vector scope, measure the level at Pin 61.
Connect an oscilloscope to pin 61 and adjust the SG4 frequency to a
frequency higher than 38.9MHz to bring the PLL into unlocked
mode. (A beat signal appears.) Lower the SG4 frequency and
measure the frequency at which the PLL locks again.
In the same manner, adjust the SG4 frequency to a lower frequency
to bring the PLL into unlocked mode. Higher the SG4 frequency
and measure the frequency at which the PLL locks again.
Determine the output level difference between carrier frequencies SIF.SYS=”00”
of 1MHz and 4.5MHz.(Reference:1MHz)
Determine the output level difference between carrier frequencies SIF.SYS=”01”
of 1MHz and 5.5MHz.(Reference:1MHz)
Determine the output level difference between carrier frequencies SIF.SYS=”10”
of 1MHz and 6.0MHz.(Reference:1MHz)
Determine the output level difference between carrier frequencies SIF.SYS=”11”
of 1MHz and 6.5MHz.(Reference:1MHz)
No.A1893-11/41
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