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M2V64S20BTP

64M bit Synchronous DRAM

MITSUBISHI ELECTRIC  

SDRAM (Rev.1.2)

Apr. '99

64M bit Synchronous DRAM

MITSUBISHI LSIs

M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)

M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)

M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)

[ Read Interrupted by Precharge ]

Burst read operation can be interrupted by precharge of the same bank . READ to PRE

interval is mini-mum 1 CLK. A PRE command to output disable latency is equivalent to

the /CAS Latency. As a result, READ to PRE interval determines valid data length to be

output. The figure below shows examples of BL=4.

Read Interrupted by Precharge (BL=4)

CLK

CL=3

Command

DQ

Command

DQ

Command

DQ

READ

PRE

Q0 Q1 Q2

READ

PRE

Q0 Q1

READ PRE

Q0

CL=2

Command

DQ

Command

DQ

Command

DQ

READ

PRE

Q0 Q1 Q2

READ

PRE

Q0 Q1

READ PRE

Q0

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