M2V64S20BTP Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC

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M2V64S20BTP

64M bit Synchronous DRAM

MITSUBISHI ELECTRIC  

SDRAM (Rev.1.2)

Apr. '99

64M bit Synchronous DRAM

MITSUBISHI LSIs

M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)

M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)

M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)

BLOCK DIAGRAM

DQ0-3 (x4)

DQ0-7 (x8)

DQ0-15 (x16)

I/O Buffer

Memory Array Memory Array Memory Array Memory Array

Bank #0

Bank #1

Bank #2

Bank #3

Mode

Register

Control Circuitry

Address Buffer

A0-11 BA0,1

Control Signal Buffer

Clock Buffer

/CS /RAS /CAS /WE DQM

CLK CKE

Type Designation Code

This rule is applied only to Synchronous DRAM families beyond 64M B-version.

M2 V 64 S 2 0 B TP - 7

Access Item

Package Type TP: TSOP(II)

Process Generation

Function 0: Random Column

Organization 2n 2: x4, 3: x8, 4: x16

Synchronous DRAM

Density 64:64M bits

Interface S: SSTL, V:LVTTL

Mitsubishi Semiconductor Memory

MITSUBISHI ELECTRIC

3

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